/*!
    \file    change log.txt
    \brief   change log for GD32G5x3 firmware

    \version 2026-02-04, V1.5.0, firmware for GD32G5x3
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.5.0 2026-02-05******************************************************************************************
______________________Common_______________________________________________________________________________________________
V1.5.0:
1. Add support for the GD32G533 series.
2. Fix compile warnings for MISRA 14.7.
3. Add support for Embedded builder. 
________________________________________________________________________________________________________________________________
______________________HRTIMER_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_hrtimer.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hrtimer.c

fix reason: Bug Fix. Add register HRTIMER_FLTRECCTL and FLTAR. Rename HRTIMER_EXEVFILTER_BLANKINGCMP1 and HRTIMER_EXEVFILTER_BLANKINGCMP3.

V1.4.0:
#define HRTIMER_ADCTRIGS3A(hrtimery)                 REG32(((hrtimery) + 0x00000380U) + 0x00000120U)                              /*!< HRTIMER trigger source 3 to ADC add register */

/* HRTIMER_STxACTL */
#define HRTIMER_STXACTL_UPBST6                        BIT(0)               /*!< update by Slave_TIMER6 update event */
#define HRTIMER_STXACTL_UPBST7                        BIT(1)               /*!< update by Slave_TIMER7 update event */
#define HRTIMER_STXACTL_DTRCFG15_9                    BITS(9,15)           /*!< rising edge dead-time value configure */
#define HRTIMER_STXACTL_DTFCFG15_9                    BITS(25,31)          /*!< falling edge dead-time value configure */

/* Slave_TIMER general behavior configuration struct definitions */
typedef struct {
    uint32_t balanced_mode;                                                 /*!< specifies whether or not the balanced mode is enabled, refer to: set balanced mode */
    uint32_t fault_enable;                                                  /*!< specifies whether or not the fault channels are enabled for the Slave_TIMER, refer to: faut channel enabled for a Slave_TIMER*/
    uint32_t fault_protect ;                                                /*!< specifies whether the write protection function is enable or not, refer to: protect fault enable */
    uint32_t deadtime_enable;                                               /*!< specifies whether or not dead time insertion is enabled for the timer, refer to: dead time enable */
    uint32_t delayed_idle;                                                  /*!< the delayed IDLE mode, refer to: set delayed IDLE state mode */
    uint32_t balanced_idle_automatic_resume;                                /*!< specifies whether or not the balanced idle automatic resumpe is enabled, refer to: balanced idle automatic resumption enable */
    uint64_t update_source;                                                 /*!< the source triggering the Slave_TIMER registers update, refer to: update is done synchronously with any other Slave_TIMER or Master_TIMER update */
    uint64_t cnt_reset;                                                     /*!< the source triggering the Slave_TIMER counter reset, refer to: Slave_TIMER counter reset */
    uint32_t reset_update;                                                  /*!< specifies whether or not registers update is triggered when the timer counter is reset, refer to: update event generated by reset event */
}hrtimer_timercfg_parameter_struct;

/* fault input configuration struct definitions */
typedef struct {
    uint32_t source;                                                        /*!< the source of the fault input, refer to: fault input source */ 
    uint32_t polarity;                                                      /*!< the polarity of the fault input, refer to: fault input polarity */ 
    uint32_t filter;                                                        /*!< fault input filter control, 0x0~0xF */ 
    uint32_t control;                                                       /*!< fault input enable or disable, refer to: enable or disable fault */ 
    uint32_t protect ;                                                      /*!< protect fault input configuration, refer to: protect fault input configuration */
    uint32_t blanksource;                                                   /*!< fault blanking source */
    uint32_t counter;                                                       /*!< fault blanking counter */
    uint32_t resetmode;                                                     /*!< fault reset mode */
    uint32_t blanksenable;                                                  /*!< fault blank enable */
}hrtimer_faultcfg_parameter_struct;

/* protect fault enable */
#define HRTIMER_STXFAULT_PROTECT_READWRITE              ((uint32_t)0x00000000U)                                          /*!< protect disable. FLTyEN (y=0..7) is writable */
#define HRTIMER_STXFAULT_PROTECT_READONLY               (HRTIMER_STXFLTCTL_FLTENPROT)                                    /*!< protect enable. FLTyEN (y=0..7) is read-only */

/* external event filter mode */
#define HRTIMER_EXEVFILTER_DISABLE                      ((uint32_t)0x00000000U)                                          /* filter mode disable */   
#define HRTIMER_EXEVFILTER_BLANKINGCMP0                 ((uint32_t)0x00000002U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP0V */
#define HRTIMER_EXEVFILTER_BLANKINGCMP1                 ((uint32_t)0x00000004U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP1V */
#define HRTIMER_EXEVFILTER_BLANKINGCMP2                 ((uint32_t)0x00000006U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP2V */
#define HRTIMER_EXEVFILTER_BLANKINGCMP3                 ((uint32_t)0x00000008U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP3V */

/* fault and event roll-over mode */
#define HRTIMER_FAULT_EVENTROLLOVER_MODE0               ((uint32_t)0x00000000U)                                          /*!< fault and event Event is generated when the counter is equal to 0 or to HRTIMER_STxCAR value */
#define HRTIMER_FAULT_EVENTROLLOVER_MODE1               ((uint32_t)0x00004000U)                                          /*!< fault and event Event is generated when the counter is equal to 0 */    
#define HRTIMER_FAULT_EVENTROLLOVER_MODE2               ((uint32_t)0x00008000U)                                          /*!< fault and event Event is generated when the counter is equal to the HRTIMER_STxCAR value */

void hrtimer_timercfg_struct_para_init(hrtimer_timercfg_parameter_struct* timercfg)
{
    timercfg->balanced_mode = HRTIMER_STXBALANCEDMODE_DISABLED;
    timercfg->balanced_idle_automatic_resume = HRTIMER_BALANE_IDLE_AUTOMATIC_RESUME_DISABLE;
    timercfg->cnt_reset = HRTIMER_STXCNT_RESET_NONE;
    timercfg->deadtime_enable = HRTIMER_STXDEADTIME_DISABLED;
    timercfg->delayed_idle = HRTIMER_STXDELAYED_IDLE_DISABLED;
    timercfg->fault_enable = HRTIMER_STXFAULTENABLE_NONE;
    timercfg->fault_protect = HRTIMER_STXFAULT_PROTECT_READWRITE;
    timercfg->reset_update = HRTIMER_STXUPDATEONRESET_DISABLED;
    timercfg->update_source = HRTIMER_STXUPDATETRIGGER_NONE;
}

void hrtimer_slavetimer_waveform_config(uint32_t hrtimer_periph, uint32_t timer_id, hrtimer_timercfg_parameter_struct * timercfg)
{
    uint32_t stxctl0_reg;
    uint32_t stxfltctl_reg;
    uint32_t stxchoctl_reg;
    uint32_t stxcntrsta_reg;
    uint32_t stxactl_reg;

    /* get the value of registers */
    stxctl0_reg = HRTIMER_STXCTL0(hrtimer_periph, timer_id);
    stxfltctl_reg = HRTIMER_STXFLTCTL(hrtimer_periph, timer_id);
    stxchoctl_reg = HRTIMER_STXCHOCTL(hrtimer_periph, timer_id);
    stxactl_reg = HRTIMER_STXACTL(hrtimer_periph, timer_id);
    
    stxcntrsta_reg = HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id);

    /* set the balanced mode */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_BLNMEN);
    stxctl0_reg |= timercfg->balanced_mode;
  
    /* update event generated by reset event */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_UPRST);
    stxctl0_reg |= timercfg->reset_update;
  
    /* set the timer update source in HRTIMER_STXCTL0 register */
    stxctl0_reg &= ~(STX_UPDATESOURCE_MASK0_5);    
    stxctl0_reg |= (uint32_t)(timercfg->update_source);
    /* set the timer update source in HRTIMER_STXACTL register */
    stxactl_reg &= ~(STX_UPDATESOURCE_MASK6_7);
    stxactl_reg |= (uint32_t)(timercfg->update_source >> 32);
    ...	
}

V1.5.0:
#define HRTIMER_ADCTRIGS3A(hrtimery)                 REG32(((hrtimery) + 0x00000380U) + 0x00000120U)                              /*!< HRTIMER trigger source 3 to ADC add register */
#define HRTIMER_FLTRECCTL(hrtimery)                  REG32(((hrtimery) + 0x00000380U) + 0x0000017CU)                              /*!< HRTIMER fault recovery control register */

/* HRTIMER_STxACTL */
#define HRTIMER_STXACTL_UPBST6                        BIT(0)               /*!< update by Slave_TIMER6 update event */
#define HRTIMER_STXACTL_UPBST7                        BIT(1)               /*!< update by Slave_TIMER7 update event */
#define HRTIMER_STXACTL_FLTAR                         BIT(8)               /*!< fault automatic resume */
#define HRTIMER_STXACTL_DTRCFG15_9                    BITS(9,15)           /*!< rising edge dead-time value configure */
#define HRTIMER_STXACTL_DTFCFG15_9                    BITS(25,31)          /*!< falling edge dead-time value configure */

/* HRTIMER_FLTRECCTL */
#define HRTIMER_FLTRECCTL_FLTRECCTL                   BIT(1)               /*!< fault recovery control */

/* Slave_TIMER general behavior configuration struct definitions */
typedef struct {
    uint32_t balanced_mode;                                                 /*!< specifies whether or not the balanced mode is enabled, refer to: set balanced mode */
    uint32_t fault_enable;                                                  /*!< specifies whether or not the fault channels are enabled for the Slave_TIMER, refer to: faut channel enabled for a Slave_TIMER*/
    uint32_t fault_protect;                                                 /*!< specifies whether the write protection function is enable or not, refer to: protect fault enable */
    uint32_t fault_automatic_resume;                                        /*!< specifies whether the fault automatic resume function is enable or not, refer to: fault automatic resume enable */
    uint32_t deadtime_enable;                                               /*!< specifies whether or not dead time insertion is enabled for the timer, refer to: dead time enable */
    uint32_t delayed_idle;                                                  /*!< the delayed IDLE mode, refer to: set delayed IDLE state mode */
    uint32_t balanced_idle_automatic_resume;                                /*!< specifies whether or not the balanced idle automatic resumpe is enabled, refer to: balanced idle automatic resumption enable */
    uint64_t update_source;                                                 /*!< the source triggering the Slave_TIMER registers update, refer to: update is done synchronously with any other Slave_TIMER or Master_TIMER update */
    uint64_t cnt_reset;                                                     /*!< the source triggering the Slave_TIMER counter reset, refer to: Slave_TIMER counter reset */
    uint32_t reset_update;                                                  /*!< specifies whether or not registers update is triggered when the timer counter is reset, refer to: update event generated by reset event */
}hrtimer_timercfg_parameter_struct;

/* fault input configuration struct definitions */
typedef struct {
    uint32_t source;                                                        /*!< the source of the fault input, refer to: fault input source */ 
    uint32_t polarity;                                                      /*!< the polarity of the fault input, refer to: fault input polarity */ 
    uint32_t filter;                                                        /*!< fault input filter control, 0x0~0xF */ 
    uint32_t control;                                                       /*!< fault input enable or disable, refer to: enable or disable fault */ 
    uint32_t protect ;                                                      /*!< protect fault input configuration, refer to: protect fault input configuration */
    uint32_t blanksource;                                                   /*!< fault blanking source */
    uint32_t counter;                                                       /*!< fault blanking counter */
    uint32_t resetmode;                                                     /*!< fault reset mode */
    uint32_t blanksenable;                                                  /*!< fault blank enable */
    uint32_t fault_recovery_control;                                        /*!< fault recovery control */
}hrtimer_faultcfg_parameter_struct;

/* protect fault enable */
#define HRTIMER_STXFAULT_PROTECT_READWRITE              ((uint32_t)0x00000000U)                                          /*!< protect disable. FLTyEN (y=0..7) is writable */
#define HRTIMER_STXFAULT_PROTECT_READONLY               (HRTIMER_STXFLTCTL_FLTENPROT)                                    /*!< protect enable. FLTyEN (y=0..7) is read-only */

/* fault automatic resume enable */
#define HRTIMER_STXFAULT_AUTOMATIC_RESUME_DISABLED      ((uint32_t)0x00000000U)                                          /*!< fault automatic resume disable */
#define HRTIMER_STXFAULT_AUTOMATIC_RESUME_ENABLED       (HRTIMER_STXACTL_FLTAR)                                          /*!< fault automatic resume enable */

/* external event filter mode */
#define HRTIMER_EXEVFILTER_DISABLE                      ((uint32_t)0x00000000U)                                          /* filter mode disable */   
#define HRTIMER_EXEVFILTER_BLANKINGCMP0                 ((uint32_t)0x00000002U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP0V */
#define HRTIMER_EXEVFILTER_WINDOWINGCMP1_WITH2          ((uint32_t)0x00000004U)                                          /*!< windowing mode. the windowing is from counter reset/roll-over to HRTIMER_STxCMP1V */
#define HRTIMER_EXEVFILTER_BLANKINGCMP2                 ((uint32_t)0x00000006U)                                          /*!< blanking mode. the blank is from counter reset/roll-over to HRTIMER_STxCMP2V */
#define HRTIMER_EXEVFILTER_WINDOWINGCMP3                ((uint32_t)0x00000008U)                                          /*!< windowing mode. the windowing is from counter reset/roll-over to HRTIMER_STxCMP3V */

/* fault and event roll-over mode */
#define HRTIMER_FAULT_EVENTROLLOVER_MODE0               ((uint32_t)0x00000000U)                                          /*!< fault and event Event is generated when the counter is equal to 0 or to HRTIMER_STxCAR value */
#define HRTIMER_FAULT_EVENTROLLOVER_MODE1               ((uint32_t)0x00004000U)                                          /*!< fault and event Event is generated when the counter is equal to 0 */    
#define HRTIMER_FAULT_EVENTROLLOVER_MODE2               ((uint32_t)0x00008000U)                                          /*!< fault and event Event is generated when the counter is equal to the HRTIMER_STxCAR value */

/* HRTIMER fault recovery control */
#define HRTIMER_FAULT_RECOVERY_CONTROL_DISABLE          ((uint32_t)0x00000000U)                                          /*!< fault counter reset on each reset / roll-over event only if no fault event is active */
#define HRTIMER_FAULT_RECOVERY_CONTROL_ENABLE           (HRTIMER_FLTRECCTL_FLTRECCTL)                                    /*!< fault counter reset on each reset / roll-over event only if no fault event happens in one period */

void hrtimer_timercfg_struct_para_init(hrtimer_timercfg_parameter_struct* timercfg)
{
    timercfg->balanced_mode = HRTIMER_STXBALANCEDMODE_DISABLED;
    timercfg->balanced_idle_automatic_resume = HRTIMER_BALANE_IDLE_AUTOMATIC_RESUME_DISABLE;
    timercfg->cnt_reset = HRTIMER_STXCNT_RESET_NONE;
    timercfg->deadtime_enable = HRTIMER_STXDEADTIME_DISABLED;
    timercfg->delayed_idle = HRTIMER_STXDELAYED_IDLE_DISABLED;
    timercfg->fault_enable = HRTIMER_STXFAULTENABLE_NONE;
    timercfg->fault_protect = HRTIMER_STXFAULT_PROTECT_READWRITE;
    timercfg->fault_automatic_resume = HRTIMER_STXFAULT_AUTOMATIC_RESUME_DISABLED;
    timercfg->reset_update = HRTIMER_STXUPDATEONRESET_DISABLED;
    timercfg->update_source = HRTIMER_STXUPDATETRIGGER_NONE;
}

void hrtimer_slavetimer_waveform_config(uint32_t hrtimer_periph, uint32_t timer_id, hrtimer_timercfg_parameter_struct * timercfg)
{
    uint32_t stxctl0_reg;
    uint32_t stxfltctl_reg;
    uint32_t stxchoctl_reg;
    uint32_t stxcntrsta_reg;
    uint32_t stxactl_reg;

    /* get the value of registers */
    stxctl0_reg = HRTIMER_STXCTL0(hrtimer_periph, timer_id);
    stxfltctl_reg = HRTIMER_STXFLTCTL(hrtimer_periph, timer_id);
    stxchoctl_reg = HRTIMER_STXCHOCTL(hrtimer_periph, timer_id);
    stxactl_reg = HRTIMER_STXACTL(hrtimer_periph, timer_id);
    
    stxcntrsta_reg = HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id);

    /* set the balanced mode */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_BLNMEN);
    stxctl0_reg |= timercfg->balanced_mode;
  
    /* update event generated by reset event */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_UPRST);
    stxctl0_reg |= timercfg->reset_update;
  
    /* set the timer update source in HRTIMER_STXCTL0 register */
    stxctl0_reg &= ~(STX_UPDATESOURCE_MASK0_5);    
    stxctl0_reg |= (uint32_t)(timercfg->update_source);
    /* set the timer update source in HRTIMER_STXACTL register */
    stxactl_reg &= ~(STX_UPDATESOURCE_MASK6_7);
    stxactl_reg |= (uint32_t)(timercfg->update_source >> 32);
    
    /* enable/disable fault automatic resume (at HRTIMER_STXACTL register) */
    stxactl_reg &= ~(HRTIMER_STXACTL_FLTAR);
    stxactl_reg |= (uint32_t)(timercfg->fault_automatic_resume);
    ...	
}

Fix file:
../Examples/HRTIMER/HRTIMER_bunch_mode/main.c

fix reason: Bug fix. Change compare_value and adjust location of hrtimer_bunchmode_software_start. Add some examples.

V1.4.0:
void hrtimer_config(void)
{
    ...
    comparecfg_para.compare_value = 1000;
    hrtimer_slavetimer_waveform_compare_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_COMPARE0, &comparecfg_para);
    comparecfg_para.compare_value = 4000;
    hrtimer_slavetimer_waveform_compare_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_COMPARE1, &comparecfg_para);
    
    hrtimer_bunchmode_struct_para_init(&bunchmode_para);
    bunchmode_para.clock_source = HRTIMER_BUNCHMODE_CLOCKSOURCE_ST0;
    bunchmode_para.idle_duration = 3;
    bunchmode_para.mode = HRTIMER_BUNCHMODE_CONTINOUS;
    bunchmode_para.period = 6;
    bunchmode_para.prescaler = HRTIMER_BUNCHMODE_PRESCALER_DIV1;
    bunchmode_para.shadow = HRTIMER_BUNCHMODEPRELOAD_DISABLED;
    bunchmode_para.trigger[0] = HRTIMER_BUNCHMODE_TRIGGER_NONE;
    hrtimer_bunchmode_config(HRTIMER0, &bunchmode_para);
    hrtimer_bunchmode_enable(HRTIMER0);
    /* bunch mode started by software */
    hrtimer_bunchmode_software_start(HRTIMER0);

    /* configure the ST0_CH0_O output of a Slave_TIMER0 work in bunch mode */
    hrtimer_channel_outputcfg_struct_para_init(&outcfg_para);
    outcfg_para.carrier_mode = HRTIMER_CHANNEL_CARRIER_DISABLED;
    outcfg_para.deadtime_bunch = HRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR;
    outcfg_para.fault_state = HRTIMER_CHANNEL_FAULTSTATE_NONE;
    outcfg_para.idle_bunch = HRTIMER_CHANNEL_BUNCH_IDLE_ENABLE;
    outcfg_para.idle_state = HRTIMER_CHANNEL_IDLESTATE_INACTIVE;
    outcfg_para.polarity = HRTIMER_CHANNEL_POLARITY_HIGH;
    outcfg_para.reset_request = HRTIMER_CHANNEL_RESET_CMP1;
    outcfg_para.set_request = HRTIMER_CHANNEL_SET_CMP0;
    hrtimer_slavetimer_waveform_channel_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_ST0_CH0, &outcfg_para);
    /* configures the ST0_CH1_O output of a Slave_TIMER0 work in waveform mode */
    outcfg_para.idle_bunch = HRTIMER_CHANNEL_BUNCH_IDLE_DISABLE;
    hrtimer_slavetimer_waveform_channel_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_ST0_CH1, &outcfg_para);

    /* enable output channel */
    hrtimer_output_channel_enable(HRTIMER0, HRTIMER_ST0_CH0);
    hrtimer_output_channel_enable(HRTIMER0, HRTIMER_ST0_CH1);
    /* enable a counter */
    hrtimer_timers_counter_enable(HRTIMER0, HRTIMER_ST0_COUNTER);
}

V1.5.0:
void hrtimer_config(void)
{
    ...
    comparecfg_para.compare_value = 2000;
    hrtimer_slavetimer_waveform_compare_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_COMPARE0, &comparecfg_para);
    comparecfg_para.compare_value = 5000;
    hrtimer_slavetimer_waveform_compare_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_COMPARE1, &comparecfg_para);
    
    hrtimer_bunchmode_struct_para_init(&bunchmode_para);
    bunchmode_para.clock_source = HRTIMER_BUNCHMODE_CLOCKSOURCE_ST0;
    bunchmode_para.idle_duration = 3;
    bunchmode_para.mode = HRTIMER_BUNCHMODE_CONTINOUS;
    bunchmode_para.period = 6;
    bunchmode_para.prescaler = HRTIMER_BUNCHMODE_PRESCALER_DIV1;
    bunchmode_para.shadow = HRTIMER_BUNCHMODEPRELOAD_DISABLED;
    bunchmode_para.trigger[0] = HRTIMER_BUNCHMODE_TRIGGER_NONE;
    hrtimer_bunchmode_config(HRTIMER0, &bunchmode_para);
    hrtimer_bunchmode_enable(HRTIMER0);

    /* configure the ST0_CH0_O output of a Slave_TIMER0 work in bunch mode */
    hrtimer_channel_outputcfg_struct_para_init(&outcfg_para);
    outcfg_para.carrier_mode = HRTIMER_CHANNEL_CARRIER_DISABLED;
    outcfg_para.deadtime_bunch = HRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR;
    outcfg_para.fault_state = HRTIMER_CHANNEL_FAULTSTATE_NONE;
    outcfg_para.idle_bunch = HRTIMER_CHANNEL_BUNCH_IDLE_ENABLE;
    outcfg_para.idle_state = HRTIMER_CHANNEL_IDLESTATE_INACTIVE;
    outcfg_para.polarity = HRTIMER_CHANNEL_POLARITY_HIGH;
    outcfg_para.reset_request = HRTIMER_CHANNEL_RESET_CMP1;
    outcfg_para.set_request = HRTIMER_CHANNEL_SET_CMP0;
    hrtimer_slavetimer_waveform_channel_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_ST0_CH0, &outcfg_para);
    /* configures the ST0_CH1_O output of a Slave_TIMER0 work in waveform mode */
    outcfg_para.idle_bunch = HRTIMER_CHANNEL_BUNCH_IDLE_DISABLE;
    hrtimer_slavetimer_waveform_channel_config(HRTIMER0, HRTIMER_SLAVE_TIMER0, HRTIMER_ST0_CH1, &outcfg_para);

    /* enable output channel */
    hrtimer_output_channel_enable(HRTIMER0, HRTIMER_ST0_CH0);
    hrtimer_output_channel_enable(HRTIMER0, HRTIMER_ST0_CH1);

    /* enable a counter */
    hrtimer_timers_counter_enable(HRTIMER0, HRTIMER_ST0_COUNTER);
    /* bunch mode started by software */
    hrtimer_bunchmode_software_start(HRTIMER0);
}

Add example HRTIMER_fault_automatic_resume AND HRTIMER_fault_software_resume.
Add example HRTIMER_frequency_conversion_output and HRTIMER_phase_shift_output.
________________________________________________________________________________________________________________________________
______________________QSPI___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_qspi.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_qspi.c
../Examples/QSPI/QSPI_Flash_Write_Read/main.c

fix reason: Add Function. Add qspi_data_length_config() function to configure the data transfer length, and modify the example to use qspi_data_length_config() to configure the data transmission length.

V1.4.0:

V1.5.0:
void qspi_data_length_config(uint32_t dtlen)
{
    if(dtlen >= 1U){
        QSPI_DTLEN = (dtlen - 1U);
    }else {
        /* do nothing */
    }
}
________________________________________________________________________________________________________________________________
______________________CAN___________________________________________________________________________________________________
Fix file:
../Examples/CAN/communication_FDmode/main.c
../Examples/CAN/communication_FDmode/gd32g5x3_it.c
../Examples/CAN/communication_classical_CAN/main.c
../Examples/CAN/communication_classical_CAN/gd32g5x3_it.c

fix reason: Bug Fix. Adjust the logic of the CAN controller for reading data. When the CAN controller reads data, it follows the sequence of reading the data first, then clearing the mailbox flag, and finally unlocking the mailbox.

V1.4.0:
void communication_check(void)
{
    uint8_t i = 0U;

    /* CAN0 receive data correctly, the received data is printed */
    if(SET == can0_receive_flag) {
        can0_receive_flag = RESET;

        /* check the receive message */
        can_mailbox_receive_data_read(CAN0, 0U, &receive_message);
        if(0U == memcmp(receive_message.data, transmit_message.data, receive_message.data_bytes)) {
            printf("\r\nCAN0 receive data: \r\n");
            for(i = 0U; i < receive_message.data_bytes; i++) {
                printf("%02x ", receive_message.data[i]);
            }
            gd_eval_led_toggle(LED1);
        }
    }
}

void CAN0_Message_IRQHandler(void)
{
    if(RESET != can_interrupt_flag_get(CAN0, CAN_INT_FLAG_MB0)) {
        can_interrupt_flag_clear(CAN0, CAN_INT_FLAG_MB0);
        can0_receive_flag = SET;
    }
}

V1.5.0:
void communication_check(void)
{
    uint8_t i = 0U;

    /* CAN0 receive data correctly, the received data is printed */
    if(SET == can0_receive_flag) {
        can0_receive_flag = RESET;
        if(0U == memcmp(receive_message.data, transmit_message.data, receive_message.data_bytes)) {
            printf("\r\nCAN0 receive data: \r\n");
            for(i = 0U; i < receive_message.data_bytes; i++) {
                printf("%02x ", receive_message.data[i]);
            }
            gd_eval_led_toggle(LED1);
        }
    }
}

extern can_mailbox_descriptor_struct receive_message;
...
void CAN0_Message_IRQHandler(void)
{
    if(RESET != can_interrupt_flag_get(CAN0, CAN_INT_FLAG_MB0)) {
        /* read the receive message */
        can_mailbox_receive_data_read(CAN0, 0U, &receive_message);
        can0_receive_flag = SET;
    }
}
________________________________________________________________________________________________________________________________
______________________GPIO___________________________________________________________________________________________________
Fix file:
../Examples/GPIO/Keyboard_polling_mode/readme.txt
../Examples/GPIO/Running_led/readme.txt

fix reason: Bug Fix. Add comments in the readme.

V1.4.0:

V1.5.0:
This example requires printing floating-point data. Please configure the "Settings->GD ARM MCU Linker->Miscellaneous" option in the Embedded Builder project and check "Use float with nano printf" to enable this functionality.
________________________________________________________________________________________________________________________________
______________________ADC___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_adc.c

fix reason: Add Function. Increase code robustness.

V1.4.0:
	ADC_SYNCCTL(ADC0) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK));
	ADC_SYNCCTL(ADC0) |= (uint32_t)prescaler;

V1.5.0:
	/* avoid some customers forget to enable because they do not use ADC0 */
	if(0U == (RCU_APB3EN & RCU_APB3EN_ADC0EN)){
		rcu_periph_clock_enable(RCU_ADC0);
	}else{
		/* illegal parameters */
	}
	ADC_SYNCCTL(ADC0) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK));
	ADC_SYNCCTL(ADC0) |= (uint32_t)prescaler;

Fix file:
../Examples/ADC/ADC0_ADC1_ADC2_routine_parallel/main.c
../Examples/ADC/ADC0_ADC1_ADC2_routine_parallel/readme.txt

fix reason: Bug Fix. Add TIMER structure initialization and resolve pin incompatibility.

V1.4.0:
	printf("\n\r ADC2: PD12, adc_value[2] = %04X \n\r",adc_value[2]);
	...
	printf("\n\r ADC2: PD13, adc_value[5] = %04X \n\r",adc_value[5]);
	...
	rcu_periph_clock_enable(RCU_GPIOC);
	rcu_periph_clock_enable(RCU_GPIOD);
	...
	gpio_mode_set(GPIOC, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0 | GPIO_PIN_1);
	gpio_mode_set(GPIOD, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_12 | GPIO_PIN_13);
	...
	adc_routine_channel_config(ADC2, 0, ADC_CHANNEL_8, 24);
	adc_routine_channel_config(ADC2, 1, ADC_CHANNEL_9, 24);
	...
	timer_oc_parameter_struct timer_ocintpara;
	timer_parameter_struct timer_initpara;

V1.5.0:
	printf("\n\r ADC2: PB0, adc_value[2] = %04X \n\r",adc_value[2]);
    ...
	printf("\n\r ADC2: PB1, adc_value[5] = %04X \n\r",adc_value[5]);
	...
	rcu_periph_clock_enable(RCU_GPIOC);
	rcu_periph_clock_enable(RCU_GPIOB);
	...
	gpio_mode_set(GPIOC, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0 | GPIO_PIN_1);
	gpio_mode_set(GPIOB, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0 | GPIO_PIN_1);
	...
	adc_routine_channel_config(ADC2, 0, ADC_CHANNEL_11, 24);
	adc_routine_channel_config(ADC2, 1, ADC_CHANNEL_0, 24);
	...
	timer_oc_parameter_struct timer_ocintpara;
	timer_parameter_struct timer_initpara;
	timer_channel_output_struct_para_init(&timer_ocintpara);
	timer_struct_para_init(&timer_initpara);

Fix file:
../Examples/ADC/ADC0_software_trigger_routine_channel_polling/main.c

fix reason: Add Function. Add COM init and output.

V1.4.0:

V1.5.0: 
int main(void)
{
    /* system clocks configuration */
    rcu_config();
    /* systick configuration */
    systick_config();
    /* configure COM port */
    gd_eval_com_init(EVAL_COM);
    /* GPIO configuration */
    gpio_config();
    /* ADC configuration */
    adc_config();

    while(1) {
        adc_value[0] = adc_channel_sample(ADC_CHANNEL_2);
        adc_value[1] = adc_channel_sample(ADC_CHANNEL_3);
        adc_value[2] = adc_channel_sample(ADC_CHANNEL_5);
        adc_value[3] = adc_channel_sample(ADC_CHANNEL_6);
        delay_1ms(1000);
        printf("\r\n //*******************************//");
        printf("\r\n ADC0 routine channel data = %04X", adc_value[0]);
        printf("\r\n ADC0 routine channel data = %04X", adc_value[1]);
        printf("\r\n ADC0 routine channel data = %04X", adc_value[2]);
        printf("\r\n ADC0 routine channel data = %04X\r\n", adc_value[3]);
    }
}
_______________________________________________________________________________________________________________________
______________________CMP___________________________________________________________________________________________________
Fix file:
../Examples/CMP/Blanking_output/main.c
../Examples/CMP/Timer0_CH0IC/main.c
../Examples/CMP/Port_output/readme.txt

fix reason: Add Function. Add TIMER structure initialization in Blanking_output and Timer0_CH0IC example. Update Port_output readme LED connection description.

V1.4.0:

V1.5.0:
void timer_config(void)
{
    ...
    timer_channel_output_struct_para_init(&timer_ocintpara);
    timer_struct_para_init(&timer_initpara);
	...
}

void timer_config(void)
{
    ...
    timer_channel_input_struct_para_init(&timer_icinitpara);
    timer_struct_para_init(&timer_init_parameter);
	...
}
________________________________________________________________________________________________________________________________
______________________SPI___________________________________________________________________________________________________
Fix file:
../Examples/SPI/SPI_master_slave_fullduplex_dma/main.c
../Examples/SPI/SPI_master_slave_fullduplex_dma/readme.txt
../Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/main.c
../Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/readme.txt
../Examples/SPI/SPI_master_slave_fullduplex_polling/main.c
../Examples/SPI/SPI_master_slave_fullduplex_polling/readme.txt
../Examples/SPI/SPI_master_slave_fullduplex_ti_mode/main.c
../Examples/SPI/SPI_master_slave_fullduplex_ti_mode/readme.txt
../Examples/SPI/SPI_master_slave_simplex_dma/main.c
../Examples/SPI/SPI_master_slave_simplex_dma/readme.txt
../Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c
../Examples/SPI/SPI_master_transmit_slave_receive_interrupt/readme.txt

fix reason: Bug Fix.

V1.4.0:
int main(void)
{
    /* initialize LED */
    gd_eval_led_init(LED1);
    gd_eval_led_init(LED2);
	...
#if SPI_CRC_ENABLE
    /* check the CRC error status  */
    if(SET != spi_flag_get(SPI0, SPI_FLAG_CRCERR)) {
        gd_eval_led_on(LED1);
    } else {
        gd_eval_led_off(LED1);
    }

    if(SET != spi_flag_get(SPI1, SPI_FLAG_CRCERR)) {
        gd_eval_led_on(LED2);
    } else {
        gd_eval_led_off(LED2);
    }
#else
    /* compare receive data with send data */
    if(ERROR != memory_compare(spi0_receive_array, spi1_send_array, ARRAYSIZE)) {
        gd_eval_led_on(LED1);
    } else {
        gd_eval_led_off(LED1);
    }
    /* compare receive data with send data */
    if(ERROR != memory_compare(spi1_receive_array, spi0_send_array, ARRAYSIZE)) {
        gd_eval_led_on(LED2);
    } else {
        gd_eval_led_off(LED2);
    }
#endif /* enable CRC function */

    SET_SPI0_NSS_HIGH

    while(1) {
    }
}

V1.5.0:
int main(void)
{
    /* initialize LED */
    gd_eval_led_init(LED1);
    gd_eval_led_init(LED3);
	...
#if SPI_CRC_ENABLE
    /* check the CRC error status  */
    if(SET != spi_flag_get(SPI0, SPI_FLAG_CRCERR)) {
        gd_eval_led_on(LED1);
    } else {
        gd_eval_led_off(LED1);
    }

    if(SET != spi_flag_get(SPI1, SPI_FLAG_CRCERR)) {
        gd_eval_led_on(LED3);
    } else {
        gd_eval_led_off(LED3);
    }
#else
    /* compare receive data with send data */
    if(ERROR != memory_compare(spi0_receive_array, spi1_send_array, ARRAYSIZE)) {
        gd_eval_led_on(LED1);
    } else {
        gd_eval_led_off(LED1);
    }
    /* compare receive data with send data */
    if(ERROR != memory_compare(spi1_receive_array, spi0_send_array, ARRAYSIZE)) {
        gd_eval_led_on(LED3);
    } else {
        gd_eval_led_off(LED3);
    }
#endif /* enable CRC function */

    SET_SPI0_NSS_HIGH

    while(1) {
    }
}

Update LED indication (LED2 -> LED3) in SPI examples and related readme.
Adjust SPI prescaler in interrupt example.
________________________________________________________________________________________________________________________________
______________________RCU___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rcu.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_rcu.c

fix reason: Bug Fix. Fix rcu_pll_clock_freq_cal() function calculation accuracy issue. Update pllpsc calculate method, add div0 condition. 

V1.4.0:
/* peripheral clock enable when sleep and deep-sleep mode*/
typedef enum
{
    /* AHB1 peripherals */
    RCU_FMC_SLP        = RCU_REGIDX_BIT(AHB1SPDPEN_REG_OFFSET, 8U),                 /*!< FMC clock when sleep and deep-sleep mode */
    ...	
	RCU_DAC3_SLP       = RCU_REGIDX_BIT(APB3SPDPEN_REG_OFFSET, 20U)                 /*!< DAC3 clock when sleep and deep-sleep mode */
}rcu_periph_sleep_enum;

static uint32_t rcu_pll_clock_freq_cal(uint32_t pllinputfreq, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_pqr)
{
    uint32_t freq;

    freq = ((uint32_t)pllinputfreq / (uint32_t)pll_psc) * ((uint32_t)pll_n );

    freq = freq / pll_pqr;

    return (uint32_t)freq;
}

uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
{
    ...
	case CK_PLLP:
        pllp_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U);
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }

        if((RCU_PLL & RCU_PLL_PLLPEN) != 0U) {
            pllp_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllp);
        }


        ck_freq = pllp_freq;
        break;
    case CK_PLLR:
        pllr_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U);
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllr = (GET_BITS(RCU_PLL, 27U, 31U));
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }

        if((RCU_PLL & RCU_PLL_PLLPEN) != 0U) {
            pllr_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllr);
        }


        ck_freq = pllr_freq;
        break;
    case CK_PLLQ:
        pllq_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U);
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllq = (GET_BITS(RCU_PLL, 23U, 26U));
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }

        if((RCU_PLL & RCU_PLL_PLLPEN) != 0U) {
            pllq_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllq);
        }


        ck_freq = pllq_freq;
        break;
    ...
}

V1.5.0:
/* peripheral clock enable when sleep and deep-sleep mode*/
typedef enum
{
    /* AHB1 peripherals */
    ...	
	RCU_DAC3_SLP       = RCU_REGIDX_BIT(APB3SPDPEN_REG_OFFSET, 20U)                 /*!< DAC3 clock when sleep and deep-sleep mode */
}rcu_periph_sleep_enum;

static uint32_t rcu_pll_clock_freq_cal(uint32_t pllinputfreq, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_pqr)
{
    float freq;

    freq = ((float)pllinputfreq / (float)pll_psc) * ((float)pll_n );

    freq = freq / (float)pll_pqr;

    return (uint32_t)freq;
}

uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
{
    ...
	case CK_PLLP:
        pllp_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U) + 1U;
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }
        if((pllpsc != 0U) && (pllp != 0U)) {
            if((RCU_PLL & RCU_PLL_PLLPEN) != 0U) {
                pllp_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllp);
            }
                }
        ck_freq = pllp_freq;
        break;
    case CK_PLLR:
        pllr_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U) + 1U;
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllr = (GET_BITS(RCU_PLL, 27U, 31U));
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }
        if((pllpsc != 0U) && (pllr != 0U)) {
            if((RCU_PLL & RCU_PLL_PLLREN) != 0U) {
                pllr_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllr);
            }
                }

        ck_freq = pllr_freq;
        break;
    case CK_PLLQ:
        pllq_freq = 0U;
        /* calculate pllp clock frequency */
        pllpsc = GET_BITS(RCU_PLL, 0U, 3U) + 1U;
        plln = (GET_BITS(RCU_PLL, 6U, 13U));
        pllq = (GET_BITS(RCU_PLL, 23U, 26U));
        /* PLL clock source selection, HXTAL or IRC8M */
        pllsel = (RCU_PLL & RCU_PLL_PLLSEL);

        if(RCU_PLLSRC_HXTAL == pllsel) {
            ck_src = HXTAL_VALUE;
        } else {
            ck_src = IRC8M_VALUE;
        }
        if((pllpsc != 0U) && (pllq != 0U)) {
            if((RCU_PLL & RCU_PLL_PLLQEN) != 0U) {
                pllq_freq = rcu_pll_clock_freq_cal(ck_src, pllpsc, plln, pllq);
            }
                }

        ck_freq = pllq_freq;
        break;
    ...
}
________________________________________________________________________________________________________________________________
______________________FWDGT__________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_fwdgt.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_fwdgt.c

fix reason: Bug Fix. Resolve the issue of PSC and RLD configurations not taking effect. Remove the definition of RLD_RLD and WND_WND from the source file to the header file.

V1.4.0:
/* write value to FWDGT_CTL_CMD bit field */
#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0U))  
/* write value to FWDGT_RLD_RLD bit field */
#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))  
/* write value to FWDGT_WND_WND bit field */
#define WND_WND(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U)) 

ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > (uint32_t)0x00000000U) && (RESET != flag_status));

    if(RESET != flag_status){
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_value;

    return SUCCESS;
} 

ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    return SUCCESS;
}

ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
    
    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_div;

    timeout = FWDGT_RLD_TIMEOUT;
    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);
    
    /* reload the counter */
    FWDGT_CTL = FWDGT_KEY_RELOAD;

    return SUCCESS;
}

V1.5.0:
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_PSC */
    FWDGT_PSC = (uint32_t)prescaler_value;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > (uint32_t)0x00000000U) && (RESET != flag_status));

    if(RESET != flag_status){
        status = ERROR;
    }

    return status;
}

ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
    /* configure FWDGT_RLD */
    FWDGT_RLD = RLD_RLD(reload_value);

    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        status = ERROR;
    }

    return status;
}

ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* start the free watchdog timer counter */
    FWDGT_CTL = FWDGT_KEY_ENABLE;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_div;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
    
    if ((uint32_t)RESET != flag_status){
        status = ERROR;
    }

    if(SUCCESS == status) {
        /* configure FWDGT_RLD */
        FWDGT_RLD = RLD_RLD(reload_value);
        /* wait until the RUD flag to be reset */
        timeout = FWDGT_RLD_TIMEOUT;
        /* wait until the RUD flag to be reset */
        do{
            flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
        }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));

        if ((uint32_t)RESET != flag_status){
            status = ERROR;
        }
    }

    if(SUCCESS == status) {
        /* reload the counter */
        FWDGT_CTL = FWDGT_KEY_RELOAD;
    }

    return status;
}
________________________________________________________________________________________________________________________________
______________________USART__________________________________________________________________________________________________
Fix file:
../Examples/USART/DMA_transmitter&receiver_interrupt/main.c
../Examples/USART/usart_transmitter&receiver_interrupt/readme.txt
../Examples/USART/IDLE_receiver_interrupt/gd32g5x3_it.c
../Examples/USART/IDLE_receiver_interrupt/main.c

fix reason: Bug Fix / Example optimization. 

V1.4.0:

V1.5.0:
Add __IO to shared variables/buffers in USART DMA_transmitter&receiver_interrupt and IDLE_receiver_interrupt example.
________________________________________________________________________________________________________________________________
______________________DMA____________________________________________________________________________________________________
Fix file:
../Examples/DMA/DMA_SYNC/readme.txt

fix reason: Update readme.

V1.4.0:
2. Repeat several times to press the Wakeup key to start another 4 DMA requests transfering

V1.5.0:
2. Repeat several times to press the Wakeup key(KEY_A) to start another 4 DMA requests transfering
________________________________________________________________________________________________________________________________
______________________TMU____________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_tmu.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_tmu.c
../Examples/TMU/sin_dma/main.c
../Examples/TMU/sin_dma/readme.txt
../Examples/TMU/sin_interrupt/main.c
../Examples/TMU/sin_interrupt/readme.txt
../Examples/TMU/sin_zero_overhead/main.c
../Examples/TMU/sin_zero_overhead/readme.txt

fix reason: Bug Fix. Remove iterations_number from tmu_parameter_struct and update the TMU examples.

V1.4.0:
/* bits definitions */
/* TMU_CS */
#define TMU_CS_MODE                 BITS(0,3)                         /*!< TMU operation mode selection */
#define TMU_CS_ITRTNUM              BITS(4,7)                         /*!< number of iterations selection */

/* TMU init parameter struct definitions */
typedef struct
{
    uint32_t mode;                                              /*!< mode of TMU operation */
    uint32_t iterations_number;                                 /*!< number of iterations selection */
    uint32_t scale;                                             /*!< scaling factor */
    uint32_t output_floating;                                   /*!< output data floating point format enable */
    uint32_t input_floating;                                    /*!< input data floating point format enable */
    uint32_t dma_read;                                          /*!< DMA request to read TMU_ODATA */
    uint32_t dma_write;                                         /*!< DMA request to write TMU_IDATA */
    uint32_t read_times;                                        /*!< times the TMU_ODATA needs to be read */
    uint32_t write_times;                                       /*!< times the TMU_IDATA needs to be write */
    uint32_t output_width;                                      /*!< width of output data */
    uint32_t input_width;                                       /*!< width of input data */
}tmu_parameter_struct;

/* TMU number of iterations definitions */
#define ITERATIONS(regval)          (BITS(4,7) & ((uint32_t)(regval) << 4))
#define TMU_ITERATION_STEPS_4       ITERATIONS(1)               /*!< 4 iteration steps */
#define TMU_ITERATION_STEPS_8       ITERATIONS(2)               /*!< 8 iteration steps */
#define TMU_ITERATION_STEPS_12      ITERATIONS(3)               /*!< 12 iteration steps */
#define TMU_ITERATION_STEPS_16      ITERATIONS(4)               /*!< 16 iteration steps */
#define TMU_ITERATION_STEPS_20      ITERATIONS(5)               /*!< 20 iteration steps */
#define TMU_ITERATION_STEPS_24      ITERATIONS(6)               /*!< 24 iteration steps */

void tmu_struct_para_init(tmu_parameter_struct* init_struct)
{
    /* set the struct with the default values */
    init_struct->mode               = TMU_MODE_COS;
    init_struct->iterations_number  = TMU_ITERATION_STEPS_20;
    init_struct->scale              = TMU_SCALING_FACTOR_1;
    init_struct->output_floating    = TMU_OUTPUT_FLOAT_DISABLE;
    init_struct->input_floating     = TMU_INPUT_FLOAT_DISABLE;
    init_struct->dma_read           = TMU_READ_DMA_DISABLE;
    init_struct->dma_write          = TMU_WRITE_DMA_DISABLE;
    init_struct->read_times         = TMU_READ_TIMES_1;
    init_struct->write_times        = TMU_WRITE_TIMES_1;
    init_struct->output_width       = TMU_OUTPUT_WIDTH_32;
    init_struct->input_width        = TMU_INPUT_WIDTH_32;
}

void tmu_init(tmu_parameter_struct* init_struct)
{
    uint32_t reg = 0U;
    reg |= ( init_struct->mode | init_struct->iterations_number | init_struct->scale |\
             init_struct->output_floating | init_struct->input_floating | init_struct->dma_read |\
             init_struct->dma_write | init_struct->read_times | init_struct->write_times |\
             init_struct->output_width | init_struct->input_width);
    TMU_CS = reg;
}

V1.5.0:
/* bits definitions */
/* TMU_CS */
#define TMU_CS_MODE                 BITS(0,3)                         /*!< TMU operation mode selection */

/* TMU init parameter struct definitions */
typedef struct
{
    uint32_t mode;                                              /*!< mode of TMU operation */
    uint32_t scale;                                             /*!< scaling factor */
    uint32_t output_floating;                                   /*!< output data floating point format enable */
    uint32_t input_floating;                                    /*!< input data floating point format enable */
    uint32_t dma_read;                                          /*!< DMA request to read TMU_ODATA */
    uint32_t dma_write;                                         /*!< DMA request to write TMU_IDATA */
    uint32_t read_times;                                        /*!< times the TMU_ODATA needs to be read */
    uint32_t write_times;                                       /*!< times the TMU_IDATA needs to be write */
    uint32_t output_width;                                      /*!< width of output data */
    uint32_t input_width;                                       /*!< width of input data */
}tmu_parameter_struct;

void tmu_struct_para_init(tmu_parameter_struct* init_struct)
{
    /* set the struct with the default values */
    init_struct->mode               = TMU_MODE_COS;
    init_struct->scale              = TMU_SCALING_FACTOR_1;
    init_struct->output_floating    = TMU_OUTPUT_FLOAT_DISABLE;
    init_struct->input_floating     = TMU_INPUT_FLOAT_DISABLE;
    init_struct->dma_read           = TMU_READ_DMA_DISABLE;
    init_struct->dma_write          = TMU_WRITE_DMA_DISABLE;
    init_struct->read_times         = TMU_READ_TIMES_1;
    init_struct->write_times        = TMU_WRITE_TIMES_1;
    init_struct->output_width       = TMU_OUTPUT_WIDTH_32;
    init_struct->input_width        = TMU_INPUT_WIDTH_32;
}

void tmu_init(tmu_parameter_struct* init_struct)
{
    uint32_t reg = 0x50U;

    reg |= ( init_struct->mode | init_struct->scale |\
             init_struct->output_floating | init_struct->input_floating | init_struct->dma_read |\
             init_struct->dma_write | init_struct->read_times | init_struct->write_times |\
             init_struct->output_width | init_struct->input_width);
    TMU_CS = reg;
}
________________________________________________________________________________________________________________________________
______________________TRIGSEL________________________________________________________________________________________________
Fix file:
../Examples/TRIGSEL/extinput_trigger_extout/main.c

fix reason: Bug Fix. Modify GPIO configuration.

V1.4.0:
int main(void)
{
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_GPIOF);
    ...
}

V1.5.0:
int main(void)
{
    rcu_periph_clock_enable(RCU_GPIOA);
    ...
}
________________________________________________________________________________________________________________________________
______________________HPDF___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_hpdf.h

fix reason: Bug Fix.

V1.4.0:
#define HPDF_FLTYEMMAX_MAXDC            BIT(0,2)
#define HPDF_FLTYEMMIN_MINDC            BIT(0,2)
#define HPDF_FLTYCT_CTCNT               BIT(4,31)

V1.5.0:
#define HPDF_FLTYEMMAX_MAXDC            BITS(0,2)
#define HPDF_FLTYEMMIN_MINDC            BITS(0,2)
#define HPDF_FLTYCT_CTCNT               BITS(4,31)
________________________________________________________________________________________________________________________________
______________________MISC___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.h

fix reason: Bug Fix.

V1.4.0:
#define MPU_ACCESS_OUTER_SHAREABLE             ((uint8_t)0x01U)

V1.5.0:
#define MPU_ACCESS_OUTER_SHAREABLE             ((uint8_t)0x02U)
________________________________________________________________________________________________________________________________
******************* V1.4.0 2025-11-15******************************************************************************************
______________________Common_______________________________________________________________________________________________
V1.4.0:
1. Add GD32EmbeddedBuilder project.
2. change the printf function to the eval.c file.
3. Add support for the GD32G533 series
________________________________________________________________________________________________________________________________
______________________DMA____________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_dma.h

fix reason: Bug Fix. 

V1.3.0:
#define DMA_REQUEST_TIMER0_TRIG            RM_CHXCFG_MUXID(49U)                            /*!< DMAMUX TIMER0 TRIG request */
#define DMA_REQUEST_TIMER0_COM             RM_CHXCFG_MUXID(50U)                            /*!< DMAMUX TIMER0 COM request */
#define DMA_REQUEST_TIMER7_TRIG            RM_CHXCFG_MUXID(60U)                            /*!< DMAMUX TIMER7 TRIG request */
#define DMA_REQUEST_TIMER7_COM             RM_CHXCFG_MUXID(61U)                            /*!< DMAMUX TIMER7 COM request */
#define DMA_REQUEST_TIMER1_TRIG            RM_CHXCFG_MUXID(67U)                            /*!< DMAMUX TIMER1 TRIG request */
#define DMA_REQUEST_TIMER3_TRIG            RM_CHXCFG_MUXID(79U)                            /*!< DMAMUX TIMER3 TRIG request */
#define DMA_REQUEST_TIMER4_TRIG            RM_CHXCFG_MUXID(85U)                            /*!< DMAMUX TIMER4 TRIG request */
#define DMA_REQUEST_TIMER14_TRIG           RM_CHXCFG_MUXID(90U)                            /*!< DMAMUX TIMER14 TRIG request */
#define DMA_REQUEST_TIMER19_TRIG           RM_CHXCFG_MUXID(107U)                           /*!< DMAMUX TIMER19 TRIG request */
#define DMA_REQUEST_TIMER19_COM            RM_CHXCFG_MUXID(108U)                           /*!< DMAMUX TIMER19 COM request */

V1.4.0:
#define DMA_REQUEST_TIMER0_TRG             RM_CHXCFG_MUXID(49U)                            /*!< DMAMUX TIMER0 TRG request */
#define DMA_REQUEST_TIMER0_CMT             RM_CHXCFG_MUXID(50U)                            /*!< DMAMUX TIMER0 CMT request */
#define DMA_REQUEST_TIMER7_TRG             RM_CHXCFG_MUXID(60U)                            /*!< DMAMUX TIMER7 TRG request */
#define DMA_REQUEST_TIMER7_CMT             RM_CHXCFG_MUXID(61U)                            /*!< DMAMUX TIMER7 CMT request */
#define DMA_REQUEST_TIMER1_TRG             RM_CHXCFG_MUXID(67U)                            /*!< DMAMUX TIMER1 TRG request */
#define DMA_REQUEST_TIMER3_TRG             RM_CHXCFG_MUXID(79U)                            /*!< DMAMUX TIMER3 TRG request */
#define DMA_REQUEST_TIMER4_TRG             RM_CHXCFG_MUXID(85U)                            /*!< DMAMUX TIMER4 TRG request */
#define DMA_REQUEST_TIMER14_TRG            RM_CHXCFG_MUXID(90U)                            /*!< DMAMUX TIMER14 TRG request */
#define DMA_REQUEST_TIMER19_TRG            RM_CHXCFG_MUXID(107U)                           /*!< DMAMUX TIMER19 TRG request */
#define DMA_REQUEST_TIMER19_CMT            RM_CHXCFG_MUXID(108U)                           /*!< DMAMUX TIMER19 CMT request */
________________________________________________________________________________________________________________________________
______________________MISC___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.h

fix reason: Merge functionality. Delete function nvic_exception_irq_enable and merge the related function to nvic_irq_enable.

V1.3.0:
nvic_irq_enable / nvic_exception_irq_enable.

V1.4.0:
nvic_irq_enable.
________________________________________________________________________________________________________________________________
______________________SPI___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_spi.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_spi.c

fix reason: Delete function.

V1.3.0:
#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_enable(uint32_t spi_periph);
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_disable(uint32_t spi_periph);

V1.4.0:
Delete marco SPI_QCTL_IO23_DRV, function spi_quad_io23_output_enable and spi_quad_io23_output_disable.
________________________________________________________________________________________________________________________________
______________________USART___________________________________________________________________________________________________
Fix file:
../Examples/USART/Synchronous/main.c

fix reason: Bug fix.

V1.3.0:
        /* wait the byte is entirely received by SPI0 */
        while(RESET == spi_flag_get(SPI0, SPI_FLAG_RXLVL_FULL)) {
        }

V1.4.0:
        /* wait the byte is entirely received by SPI0 */
        while(RESET == spi_flag_get(SPI0, SPI_FLAG_RBNE)) {
        }
________________________________________________________________________________________________________________________________
______________________PMU___________________________________________________________________________________________________
Fix file:
../Examples/PMU/Deepsleep_wakeup_RTC/main.c
../Examples/PMU/Deepsleep_wakeup_exti/main.c
../Examples/PMU/Standby_wakeup_RTC/main.c
../Examples/PMU/Standby_wakeup_pin/main.c

fix reason: Bug fix.

V1.3.0:

V1.4.0:

Add frequency switching logic.
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}
________________________________________________________________________________________________________________________________
______________________CAU___________________________________________________________________________________________________
Fix file:
../Examples/CAU/CAU_AESECB_mode/main.c
../Examples/CAU/CAU_AESECB_mode/main.h
../Examples/CAU/CAU_AES_GCM_CCM_CFB_OFB_mode/main.c
../Examples/CAU/CAU_AES_GCM_CCM_CFB_OFB_mode/main.h
../Examples/CAU/CAU_AES_modes/main.c
../Examples/CAU/CAU_AES_modes/main.h
../Examples/CAU/CAU_DES_TDES_modes/main.c
../Examples/CAU/CAU_DES_TDES_modes/main.h
../Examples/CAU/CAU_TDESECB_mode/main.c
../Examples/CAU/CAU_TDESECB_mode/main.h

fix reason: Bug fix.

V1.3.0:

V1.4.0:
Modify the data aligned width.
________________________________________________________________________________________________________________________________
______________________HPDF___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hpdf.c

fix reason: Bug fix.

V1.3.0:
void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
{
.......
    init_struct->mm_break_signal        = DISABLE;
.......
}

V1.4.0:
void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
{
.......
    init_struct->mm_break_signal        = NO_MM_BREAK;
.......
}
________________________________________________________________________________________________________________________________
______________________TIMER___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_timer.h

fix reason: Bug Fix. 

V1.3.0:
#define TIMER_INITIAL_DIRECTION_DOWN        ((uint32_t)0x00000000U)                 /*!< counter count down when synchronization event occurs */
#define TIMER_INITIAL_DIRECTION_UP          TIMER_CINITCTL_CINITDIR                 /*!< counter count up when synchronization event occurs */

V1.4.0:
#define TIMER_INITIAL_DIRECTION_UP        ((uint32_t)0x00000000U)                      /*!< counter count down when synchronization event occurs */
#define TIMER_INITIAL_DIRECTION_DOWN          TIMER_CINITCTL_CINITDIR         /*!< counter count up when synchronization event occurs  */
___________________________________________________________________________________________________________________________
******************* V1.3.0 2025-08-07******************************************************************************************
______________________Common_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_misc.c

fix reason: Bug Fix. Modify the initial parameters of the initialization function

V1.2.0:
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct)
{
    attribute_init_struct->attribute_number = MPU_REGION_NUMBER0;
    attribute_init_struct->memory_type      = MPU_OUTER_DEVICE;
    attribute_init_struct->inner_attributes = MPU_DEVICE_nGnRnE;
    attribute_init_struct->outer_attributes = 0U;
}

V1.3.0:
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct)
{
    attribute_init_struct->attribute_number = MPU_ATTRIBUTE_NUMBER0;
    attribute_init_struct->memory_type      = MPU_MEMORY_DEVICE;
    attribute_init_struct->inner_attributes = MPU_DEVICE_nGnRnE;
    attribute_init_struct->outer_attributes = MPU_OUTER_DEVICE;
}
____________________________________________________________________________________________________________________________
______________________Common_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_misc.c

fix reason: Add function.

V1.2.0:
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, 
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
    /* use the priority group value to get the temp_pre and the temp_sub */
    if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
        temp_pre=0U;
        temp_sub=0x4U;
    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
        temp_pre=1U;
        temp_sub=0x3U;
    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
        temp_pre=2U;
        temp_sub=0x2U;
    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
        temp_pre=3U;
        temp_sub=0x1U;
    }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
        temp_pre=4U;
        temp_sub=0x0U;
    }else{
        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
        temp_pre=2U;
        temp_sub=0x2U;
    }
    /* get the temp_priority to fill the NVIC->IP register */
    temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
    temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
    temp_priority = temp_priority << 0x04U;
    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
    /* enable the selected IRQ */
    NVIC->ISER[(uint8_t)nvic_irq >> 0x05U] = (uint32_t)0x01U << ((uint8_t)nvic_irq & (uint8_t)0x1FU);
}

1.3.0:
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, 
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
    if((int)nvic_irq < (int)0U){
        /* do nothing, should not be here */
    }else{
        /* use the priority group value to get the temp_pre and the temp_sub */
        if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
            temp_pre=0U;
            temp_sub=0x4U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
            temp_pre=1U;
            temp_sub=0x3U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
            temp_pre=2U;
            temp_sub=0x2U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
            temp_pre=3U;
            temp_sub=0x1U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
            temp_pre=4U;
            temp_sub=0x0U;
        }else{
            nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
            temp_pre=2U;
            temp_sub=0x2U;
        }
        /* get the temp_priority to fill the NVIC->IP register */
        temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
        temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
        temp_priority = temp_priority << 0x04U;
        NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
        /* enable the selected IRQ */
        NVIC->ISER[(uint8_t)nvic_irq >> 0x05U] = (uint32_t)0x01U << ((uint8_t)nvic_irq & (uint8_t)0x1FU);
    }
}

/*!
    \brief      enable Cortex-M33 NVIC request
    \param[in]  nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
                the parameter should be less than 0
    \param[in]  nvic_irq_pre_priority: the pre-emption priority needed to set
    \param[in]  nvic_irq_sub_priority: the subpriority needed to set
    \param[out] none
    \retval     none
*/
void nvic_exception_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, 
                               uint8_t nvic_irq_sub_priority)
{
    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
    if((int)nvic_irq < 0U){
        /* use the priority group value to get the temp_pre and the temp_sub */
        if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
            temp_pre=0U;
            temp_sub=0x4U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
            temp_pre=1U;
            temp_sub=0x3U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
            temp_pre=2U;
            temp_sub=0x2U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
            temp_pre=3U;
            temp_sub=0x1U;
        }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
            temp_pre=4U;
            temp_sub=0x0U;
        }else{
            nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
            temp_pre=2U;
            temp_sub=0x2U;
        }
        /* get the temp_priority to fill the NVIC->IP register */
        temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
        temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
        temp_priority = temp_priority << 0x04U;
        SCB->SHPR[(((uint32_t)nvic_irq) & 0xFU) - 0x4U] = (uint8_t)temp_priority;
    }else{
        /* do nothing, should not be here */
    }
}
____________________________________________________________________________________________________________________________
______________________TIMER_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_timer.c

fix reason: Bug Fix.

V1.2.0:
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
{
    if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || (TIMER19 == timer_periph)) {
        TIMER_CCHP0(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
                                               ((uint32_t)(breakpara->ideloffstate)) |
                                               ((uint32_t)(breakpara->deadtime)) |
                                               ((uint32_t)(breakpara->outputautostate)) |
                                               ((uint32_t)(breakpara->protectmode)) |
                                               ((uint32_t)(breakpara->break0state)) |
                                               ((uint32_t)(breakpara->break0filter)) |
                                               ((uint32_t)(breakpara->break0polarity)) |
                                               ((uint32_t)(breakpara->break0lock)) |
                                               ((uint32_t)(breakpara->break0release)) |
                                               ((uint32_t)(breakpara->break1state)) |
                                               ((uint32_t)(breakpara->break1filter)) |
                                               ((uint32_t)(breakpara->break1polarity)) |
                                               ((uint32_t)(breakpara->break1lock)) |
                                               ((uint32_t)(breakpara->break1release)));
    } else if((TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) {
        TIMER_CCHP0(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
                                               ((uint32_t)(breakpara->ideloffstate)) |
                                               ((uint32_t)(breakpara->deadtime)) |
                                               ((uint32_t)(breakpara->outputautostate)) |
                                               ((uint32_t)(breakpara->protectmode)) |
                                               ((uint32_t)(breakpara->break0state)) |
                                               ((uint32_t)(breakpara->break0filter)) |
                                               ((uint32_t)(breakpara->break0polarity)) |
                                               ((uint32_t)(breakpara->break0lock)) |
                                               ((uint32_t)(breakpara->break0release)));
    } else {
        /* illegal parameters */
    }
}

V1.3.0:
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
{
    if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || (TIMER19 == timer_periph)) {
        TIMER_CCHP0(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
                                               ((uint32_t)(breakpara->ideloffstate)) |
                                               ((uint32_t)(breakpara->deadtime)) |
                                               ((uint32_t)(breakpara->outputautostate)) |
                                               ((uint32_t)(breakpara->protectmode)) |
                                               ((uint32_t)(breakpara->break0state)) |
                                               ((uint32_t)(breakpara->break0filter) << 16) |
                                               ((uint32_t)(breakpara->break0polarity)) |
                                               ((uint32_t)(breakpara->break0lock)) |
                                               ((uint32_t)(breakpara->break0release)) |
                                               ((uint32_t)(breakpara->break1state)) |
                                               ((uint32_t)(breakpara->break1filter) << 20) |
                                               ((uint32_t)(breakpara->break1polarity)) |
                                               ((uint32_t)(breakpara->break1lock)) |
                                               ((uint32_t)(breakpara->break1release)));
    } else if((TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) {
        TIMER_CCHP0(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
                                               ((uint32_t)(breakpara->ideloffstate)) |
                                               ((uint32_t)(breakpara->deadtime)) |
                                               ((uint32_t)(breakpara->outputautostate)) |
                                               ((uint32_t)(breakpara->protectmode)) |
                                               ((uint32_t)(breakpara->break0state)) |
                                               ((uint32_t)(breakpara->break0filter) << 16) |
                                               ((uint32_t)(breakpara->break0polarity)) |
                                               ((uint32_t)(breakpara->break0lock)) |
                                               ((uint32_t)(breakpara->break0release)));
    } else {
        /* illegal parameters */
    }
}
____________________________________________________________________________________________________________________________
______________________HRTIMER_______________________________________________________________________________________________
Fix file:
../Examples/HRTIMER/HRTIMER_exchange_output/main.c

fix reason: Bug Fix.

V1.2.0:
timercfg_para.cnt_reset = HRTIMER_STXCNT_RESET_CMP3;

V1.3.0:
timercfg_para.cnt_reset = HRTIMER_STXCNT_RESET_NONE;
____________________________________________________________________________________________________________________________
______________________HRTIMER_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hrtimer.c

fix reason: Bug Fix. Fix hrtimer_fault_config HRTIMER_FAULT_5 protect configuration.

V1.2.0:
            /* configure fault input 5 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT5INP | HRTIMER_FLTINCFG1_FLT5INSRC0 | HRTIMER_FLTINCFG1_FLT5INSRC1 | HRTIMER_FLTINCFG1_FLT5INFC | HRTIMER_FLTINCFG1_FLT5INPROT | HRTIMER_FLTINCFG1_FLT5INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG1_FLT5INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 20) & HRTIMER_FLTINCFG1_FLT5INSRC1);
            fltincfg1 |= (faultcfg->polarity << 8);
            fltincfg1 |= ((faultcfg->filter) << 11);
            fltincfg1 |= ((faultcfg->control) << 8);
            fltincfg1 |= faultcfg->protect;

V1.3.0:
            /* configure fault input 5 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT5INP | HRTIMER_FLTINCFG1_FLT5INSRC0 | HRTIMER_FLTINCFG1_FLT5INSRC1 | HRTIMER_FLTINCFG1_FLT5INFC | HRTIMER_FLTINCFG1_FLT5INPROT | HRTIMER_FLTINCFG1_FLT5INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG1_FLT5INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 20) & HRTIMER_FLTINCFG1_FLT5INSRC1);
            fltincfg1 |= (faultcfg->polarity << 8);
            fltincfg1 |= ((faultcfg->filter) << 11);
            fltincfg1 |= ((faultcfg->control) << 8);
            fltincfg1 |= ((faultcfg->protect) << 8);
____________________________________________________________________________________________________________________________
______________________USART_______________________________________________________________________________________________
Fix file:
../Examples/USART/Half_duplex_transmitter&receiver/main.c

fix reason: Bug Fix. Update UART half-duplex transmission pin to internal pull-up open-drain mode.

V1.2.0:
    /* enable USART and GPIOA clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_USART0);
    rcu_periph_clock_enable(RCU_USART1);

    /* configure the USART0 TX pin and USART1 TX pin */
    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_2);
    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9);
    /* configure USART0 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_2);

V1.3.0:
    /* enable USART GPIOA GPIOD clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_GPIOD);
    rcu_periph_clock_enable(RCU_USART0);
    rcu_periph_clock_enable(RCU_USART1);

    /* configure the USART0 TX pin and USART1 TX pin */
    gpio_af_set(GPIOD, GPIO_AF_7, GPIO_PIN_5);
    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9);
    /* configure USART0 TX as alternate function open-drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_100_220MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function open-drain */
    gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_5);
    gpio_output_options_set(GPIOD, GPIO_OTYPE_OD, GPIO_OSPEED_100_220MHZ, GPIO_PIN_5);

 V1.2.0:
    usart_data_receive(USART0);

    /* USART1 transmit and USART0 receive*/
    while(transfersize1--) {
        /* wait until end of transmit */
        while(RESET == usart_flag_get(USART1, USART_FLAG_TBE)) {
        }

        usart_data_transmit(USART1, transmitter_buffer1[txcount1++]);

        while(RESET == usart_flag_get(USART0, USART_FLAG_RBNE)) {
        }

        /* store the received byte in the receiver_buffer0 */
        receiver_buffer0[rxcount1++] = usart_data_receive(USART0);
    }

    /* compare the received data with the send ones */
    state1 = memory_compare(transmitter_buffer0, receiver_buffer0, TRANSMIT_SIZE0);
    state2 = memory_compare(transmitter_buffer1, receiver_buffer0, TRANSMIT_SIZE1);

V1.3.0:
    /* compare the received data with the send ones */
    state1 = memory_compare(transmitter_buffer0, receiver_buffer1, TRANSMIT_SIZE0);
    usart_data_receive(USART0);

    /* USART1 transmit and USART0 receive*/
    while(transfersize1--) {
        /* wait until end of transmit */
        while(RESET == usart_flag_get(USART1, USART_FLAG_TBE)) {
        }

        usart_data_transmit(USART1, transmitter_buffer1[txcount1++]);

        while(RESET == usart_flag_get(USART0, USART_FLAG_RBNE)) {
        }

        /* store the received byte in the receiver_buffer0 */
        receiver_buffer0[rxcount1++] = usart_data_receive(USART0);
    }

    /* compare the received data with the send ones */
    state2 = memory_compare(transmitter_buffer1, receiver_buffer0, TRANSMIT_SIZE1);
____________________________________________________________________________________________________________________________
______________________HPDF_______________________________________________________________________________________________
Fix file:
../Examples/HRTIMER/HRTIMER_exchange_output/main.c

fix reason: Bug Fix. Modify hpdf_clock_output_config() funtion, Repeatedly clear HPDF_CH0CTL_CKOUTSEL, without clearing HPDF_CH0CTL_CKOUTDIV.

V1.2.0:
void hpdf_clock_output_config(uint32_t source, uint8_t divider, uint32_t mode)
{
    uint32_t reg;
    reg = HPDF_CHXCTL(CHANNEL0);
    reg &= ~(HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTDM);
    /* configure serial output clock */
    reg |= (source | ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET) | mode);
    HPDF_CHXCTL(CHANNEL0) = reg;
}

V1.3.0:
void hpdf_clock_output_config(uint32_t source, uint8_t divider, uint32_t mode)
{
    uint32_t reg;
    reg = HPDF_CHXCTL(CHANNEL0);
    reg &= ~(HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTDIV | HPDF_CH0CTL_CKOUTDM);
    /* configure serial output clock */
    reg |= (source | ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET) | mode);
    HPDF_CHXCTL(CHANNEL0) = reg;
}
____________________________________________________________________________________________________________________________
______________________HPDF_______________________________________________________________________________________________
Fix file:
../Examples/HPDF/sample_internal_parallel_data&inserted_conversion/main.c

fix reason: Bug Fix. 

V1.2.0:
void dma_config(void)
{
    dma_parameter_struct dma_init_parameter;

    /* deinitialize DMA1_CH1 */
    dma_deinit(DMA1, DMA_CH1);
    dma_struct_para_init(&dma_init_parameter);

    /* configure DMA1_CH1 */
    dma_init_parameter.request =  DMA_REQUEST_HPDF_FLT0;
    dma_init_parameter.periph_addr = (int32_t)&HPDF_FLTYIDATA(FLT0);
    dma_init_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_parameter.memory_addr = (uint32_t)conversion_data;
    dma_init_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_parameter.periph_width = DMA_PERIPHERAL_WIDTH_32BIT;
    dma_init_parameter.direction = DMA_PERIPHERAL_TO_MEMORY;
    dma_init_parameter.number = HPDF_OUTPUT_BUFFER;
    dma_init_parameter.priority = DMA_PRIORITY_ULTRA_HIGH;
    dma_init(DMA1, DMA_CH1, &dma_init_parameter);
    dma_circulation_disable(DMA1, DMA_CH1);
}

V1.3.0:
void dma_config(void)
{
    dma_parameter_struct dma_init_parameter;

    /* deinitialize DMA1_CH1 */
    dma_deinit(DMA1, DMA_CH1);
    dma_struct_para_init(&dma_init_parameter);

    /* configure DMA1_CH1 */
    dma_init_parameter.request =  DMA_REQUEST_HPDF_FLT0;
    dma_init_parameter.periph_addr = (int32_t)&HPDF_FLTYIDATA(FLT0);
    dma_init_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_parameter.memory_addr = (uint32_t)conversion_data;
    dma_init_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_parameter.periph_width = DMA_PERIPHERAL_WIDTH_32BIT;
    dma_init_parameter.memory_width = DMA_MEMORY_WIDTH_32BIT;
    dma_init_parameter.direction = DMA_PERIPHERAL_TO_MEMORY;
    dma_init_parameter.number = HPDF_OUTPUT_BUFFER;
    dma_init_parameter.priority = DMA_PRIORITY_ULTRA_HIGH;
    dma_init(DMA1, DMA_CH1, &dma_init_parameter);
    dma_circulation_disable(DMA1, DMA_CH1);
}
____________________________________________________________________________________________________________________________
______________________TIMER_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_timer.h

fix reason: Bug Fix. 

V1.2.0:
#define TIMER_DMACFG_DMATA_FCCHP0           DMACFG_DMATA(30)                        /*!< DMA transfer address is TIMER_FCCHP0 */
#define TIMER_DMACFG_DMATA_FCCHP1           DMACFG_DMATA(31)                        /*!< DMA transfer address is TIMER_FCCHP1 */
#define TIMER_DMACFG_DMATA_FCCHP2           DMACFG_DMATA(32)                        /*!< DMA transfer address is TIMER_FCCHP2 */
#define TIMER_DMACFG_DMATA_FCCHP3           DMACFG_DMATA(33)                        /*!< DMA transfer address is TIMER_FCCHP3 */
#define TIMER_DMACFG_DMATA_AFCTL0           DMACFG_DMATA(34)                        /*!< DMA transfer address is TIMER_AFCTL0 */
#define TIMER_DMACFG_DMATA_AFCTL1           DMACFG_DMATA(35)                        /*!< DMA transfer address is TIMER_AFCTL1 */
#define TIMER_DMACFG_DMATA_WDGPER           DMACFG_DMATA(36)                        /*!< DMA transfer address is TIMER_WDGPER */
#define TIMER_DMACFG_DMATA_CREP1            DMACFG_DMATA(37)                        /*!< DMA transfer address is TIMER_CREP1 */
#define TIMER_DMACFG_DMATA_CCHP1            DMACFG_DMATA(38)                        /*!< DMA transfer address is TIMER_CCHP1 */
#define TIMER_DMACFG_DMATA_DECCTL           DMACFG_DMATA(39)                        /*!< DMA transfer address is TIMER_DECCTL */
#define TIMER_DMACFG_DMATA_CINITCTL         DMACFG_DMATA(40)                        /*!< DMA transfer address is TIMER_CINITCTL */
#define TIMER_DMACFG_DMATA_CINITV           DMACFG_DMATA(41)                        /*!< DMA transfer address is TIMER_CINITV */

V1.3.0:
#define TIMER_DMACFG_DMATA_FCCHP0           DMACFG_DMATA(31)                        /*!< DMA transfer address is TIMER_FCCHP0 */
#define TIMER_DMACFG_DMATA_FCCHP1           DMACFG_DMATA(32)                        /*!< DMA transfer address is TIMER_FCCHP1 */
#define TIMER_DMACFG_DMATA_FCCHP2           DMACFG_DMATA(33)                        /*!< DMA transfer address is TIMER_FCCHP2 */
#define TIMER_DMACFG_DMATA_FCCHP3           DMACFG_DMATA(34)                        /*!< DMA transfer address is TIMER_FCCHP3 */
#define TIMER_DMACFG_DMATA_AFCTL0           DMACFG_DMATA(35)                        /*!< DMA transfer address is TIMER_AFCTL0 */
#define TIMER_DMACFG_DMATA_AFCTL1           DMACFG_DMATA(36)                        /*!< DMA transfer address is TIMER_AFCTL1 */
#define TIMER_DMACFG_DMATA_WDGPER           DMACFG_DMATA(37)                        /*!< DMA transfer address is TIMER_WDGPER */
#define TIMER_DMACFG_DMATA_CREP1            DMACFG_DMATA(38)                        /*!< DMA transfer address is TIMER_CREP1 */
#define TIMER_DMACFG_DMATA_CCHP1            DMACFG_DMATA(39)                        /*!< DMA transfer address is TIMER_CCHP1 */
#define TIMER_DMACFG_DMATA_DECCTL           DMACFG_DMATA(40)                        /*!< DMA transfer address is TIMER_DECCTL */
#define TIMER_DMACFG_DMATA_CINITCTL         DMACFG_DMATA(41)                        /*!< DMA transfer address is TIMER_CINITCTL */
#define TIMER_DMACFG_DMATA_CINITV           DMACFG_DMATA(42)                        /*!< DMA transfer address is TIMER_CINITV */
____________________________________________________________________________________________________________________________
______________________CAN___________________________________________________________________________________________________
Fix file:
../Examples/CAN/communication_FDmode/main.c

fix reason: Bug Fix. Update the CANFD baud rate parameter

V1.2.0:
void can_config(void)
{
    can_parameter_struct can_parameter;
    can_fd_parameter_struct fd_parameter;

    /* select CK_APB2 as CAN's clock source */
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2);
    /* enable CAN clock */
    rcu_periph_clock_enable(RCU_CAN0);
    rcu_periph_clock_enable(RCU_CAN1);
    /* initialize CAN register */
    can_deinit(CAN0);
    can_deinit(CAN1);
    /* initialize CAN */
    can_struct_para_init(CAN_INIT_STRUCT, &can_parameter);
    can_struct_para_init(CAN_FD_INIT_STRUCT, &fd_parameter);

    /* initialize CAN parameters */
    can_parameter.internal_counter_source = CAN_TIMER_SOURCE_BIT_CLOCK;
    can_parameter.self_reception = DISABLE;
    can_parameter.mb_tx_order = CAN_TX_HIGH_PRIORITY_MB_FIRST;
    can_parameter.mb_tx_abort_enable = ENABLE;
    can_parameter.local_priority_enable = DISABLE;
    can_parameter.mb_rx_ide_rtr_type = CAN_IDE_RTR_FILTERED;
    can_parameter.mb_remote_frame = CAN_STORE_REMOTE_REQUEST_FRAME;
    can_parameter.rx_private_filter_queue_enable = DISABLE;
    can_parameter.edge_filter_enable = DISABLE;
    can_parameter.protocol_exception_enable = DISABLE;
    can_parameter.rx_filter_order = CAN_RX_FILTER_ORDER_MAILBOX_FIRST;
    can_parameter.memory_size = CAN_MEMSIZE_32_UNIT;
    /* filter configuration */
    can_parameter.mb_public_filter = 0U;
    /* baud rate 1Mbps */
    can_parameter.resync_jump_width = 1U;
    can_parameter.prop_time_segment = 2U;
    can_parameter.time_segment_1 = 4U;
    can_parameter.time_segment_2 = 1U;
    can_parameter.prescaler = 27U;

    /* initialize CAN */
    can_init(CAN0, &can_parameter);
    can_init(CAN1, &can_parameter);

    /* FD parameter configurations */
    fd_parameter.bitrate_switch_enable = ENABLE;
    fd_parameter.iso_can_fd_enable = ENABLE;
    fd_parameter.mailbox_data_size = CAN_MAILBOX_DATA_SIZE_64_BYTES;
    fd_parameter.tdc_enable = DISABLE;
    fd_parameter.tdc_offset = 0U;
    /* FD baud rate 1Mbps */
    fd_parameter.resync_jump_width = 1U;
    fd_parameter.prop_time_segment = 2U;
    fd_parameter.time_segment_1 = 4U;
    fd_parameter.time_segment_2 = 1U;
    fd_parameter.prescaler = 27U;

    can_fd_config(CAN0, &fd_parameter);
    can_fd_config(CAN1, &fd_parameter);

    /* configure CAN0 NVIC */
    nvic_irq_enable(CAN0_Message_IRQn, 0U, 0U);

    /* enable CAN MB0 interrupt */
    can_interrupt_enable(CAN0, CAN_INT_MB0);

    can_operation_mode_enter(CAN1, CAN_NORMAL_MODE);
    can_operation_mode_enter(CAN0, CAN_NORMAL_MODE);
}

V1.3.0:
void can_config(void)
{
    can_parameter_struct can_parameter;
    can_fd_parameter_struct fd_parameter;

    /* select CK_APB2 as CAN's clock source */
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2);
    /* enable CAN clock */
    rcu_periph_clock_enable(RCU_CAN0);
    rcu_periph_clock_enable(RCU_CAN1);
    /* initialize CAN register */
    can_deinit(CAN0);
    can_deinit(CAN1);
    /* initialize CAN */
    can_struct_para_init(CAN_INIT_STRUCT, &can_parameter);
    can_struct_para_init(CAN_FD_INIT_STRUCT, &fd_parameter);

    /* initialize CAN parameters */
    can_parameter.internal_counter_source = CAN_TIMER_SOURCE_BIT_CLOCK;
    can_parameter.self_reception = DISABLE;
    can_parameter.mb_tx_order = CAN_TX_HIGH_PRIORITY_MB_FIRST;
    can_parameter.mb_tx_abort_enable = ENABLE;
    can_parameter.local_priority_enable = DISABLE;
    can_parameter.mb_rx_ide_rtr_type = CAN_IDE_RTR_FILTERED;
    can_parameter.mb_remote_frame = CAN_STORE_REMOTE_REQUEST_FRAME;
    can_parameter.rx_private_filter_queue_enable = DISABLE;
    can_parameter.edge_filter_enable = DISABLE;
    can_parameter.protocol_exception_enable = DISABLE;
    can_parameter.rx_filter_order = CAN_RX_FILTER_ORDER_MAILBOX_FIRST;
    can_parameter.memory_size = CAN_MEMSIZE_32_UNIT;
    /* filter configuration */
    can_parameter.mb_public_filter = 0U;
    /* baud rate 1Mbps */
    can_parameter.resync_jump_width = 1U;
    can_parameter.prop_time_segment = 2U;
    can_parameter.time_segment_1 = 7U;
    can_parameter.time_segment_2 = 2U;
    can_parameter.prescaler = 18U;

    /* initialize CAN */
    can_init(CAN0, &can_parameter);
    can_init(CAN1, &can_parameter);

    /* FD parameter configurations */
    fd_parameter.bitrate_switch_enable = ENABLE;
    fd_parameter.iso_can_fd_enable = ENABLE;
    fd_parameter.mailbox_data_size = CAN_MAILBOX_DATA_SIZE_64_BYTES;
    fd_parameter.tdc_enable = DISABLE;
    fd_parameter.tdc_offset = 0U;
    /* FD baud rate 1Mbps */
    fd_parameter.resync_jump_width = 1U;
    fd_parameter.prop_time_segment = 2U;
    fd_parameter.time_segment_1 = 7U;
    fd_parameter.time_segment_2 = 2U;
    fd_parameter.prescaler = 18U;

    can_fd_config(CAN0, &fd_parameter);
    can_fd_config(CAN1, &fd_parameter);

    /* configure CAN0 NVIC */
    nvic_irq_enable(CAN0_Message_IRQn, 0U, 0U);

    /* enable CAN MB0 interrupt */
    can_interrupt_enable(CAN0, CAN_INT_MB0);

    can_operation_mode_enter(CAN1, CAN_NORMAL_MODE);
    can_operation_mode_enter(CAN0, CAN_NORMAL_MODE);
}
____________________________________________________________________________________________________________________________
______________________HRTIMER_______________________________________________________________________________________________
Fix file:
../Examples/HRTIMER/HRTIMER_input_capture/main.c

fix reason: Bug Fix. Change baseinit_para.period = 0xFFFF to baseinit_para.period = 0xFFFE in function hrtimer_config.

V1.2.0:
baseinit_para.period = 0xFFFF;

V1.3.0:
baseinit_para.period = 0xFFFE;
____________________________________________________________________________________________________________________________
______________________PMU___________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_pmu.c

fix reason: Bug Fix.

V1.2.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __WFE();
        __WFE();
    }
}

V1.3.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __SEV();
        __WFE();
        __WFE();
    }
}
____________________________________________________________________________________________________________________________
______________________TIMER_______________________________________________________________________________________________
Fix file:
../Examples/TIMER/TIMER0_deadtime_break/main.c

fix reason: Bug Fix.

V1.2.0:
    timer_multi_mode_channel_mode_config(TIMER0, TIMER_CH_0, TIMER_MCH_MODE_COMPLEMENTARY);
    timer_multi_mode_channel_mode_config(TIMER0, TIMER_CH_1, TIMER_MCH_MODE_COMPLEMENTARY);

V1.3.0:
    timer_multi_mode_channel_mode_config(TIMER0, TIMER_MCH_0, TIMER_MCH_MODE_COMPLEMENTARY);
    timer_multi_mode_channel_mode_config(TIMER0, TIMER_MCH_1, TIMER_MCH_MODE_COMPLEMENTARY);
____________________________________________________________________________________________________________________________
______________________TMU_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_tmu.c

fix reason: Bug Fix. Adapt to GCC compilation environment.

V1.2.0:
void tmu_one_f32_read(float* p)
{
    *p = *((float *)(uint32_t)(&TMU_ODATA));
}
void tmu_two_f32_read(float* p1, float* p2)
{
    *p1 = *((float *)(uint32_t)(&TMU_ODATA));
    *p2 = *((float *)(uint32_t)(&TMU_ODATA));
}
void tmu_one_f32_write(float data)
{
    TMU_IDATA = *((uint32_t *)(&data));
}
void tmu_two_f32_write(float data1, float data2)
{
    TMU_IDATA = *((uint32_t *)(&data1));
    TMU_IDATA = *((uint32_t *)(&data2));
}
void tmu_one_f32_read(float* p)
{
    uint32_t data;
    data = TMU_ODATA;
    *p = *((float *)(uint32_t)(&data));
}
void tmu_two_f32_read(float* p1, float* p2)
{
    uint32_t data;
    data = TMU_ODATA;
    *p1 = *((float *)(uint32_t)(&data));
    data = TMU_ODATA;
    *p2 = *((float *)(uint32_t)(&data));
}

V1.3.0:
void tmu_one_f32_read(float* p)
{
    uint32_t data;
    data = TMU_ODATA;
    *p = *((float *)(uint32_t)(&data));
}
void tmu_two_f32_read(float* p1, float* p2)
{
    uint32_t data;
    data = TMU_ODATA;
    *p1 = *((float *)(uint32_t)(&data));
    data = TMU_ODATA;
    *p2 = *((float *)(uint32_t)(&data));
}
void tmu_one_f32_write(float data)
{
    TMU_IDATA_FLOAT = (float)data;
}
void tmu_two_f32_write(float data1, float data2)
{
    TMU_IDATA_FLOAT = (float)data1;
    TMU_IDATA_FLOAT = (float)data2;
}
void tmu_one_f32_read(float* p)
{
    *p = (float)TMU_ODATA_FLOAT;
}
void tmu_two_f32_read(float* p1, float* p2)
{
    *p1 = (float)TMU_ODATA_FLOAT;
    *p2 = (float)TMU_ODATA_FLOAT;
}
____________________________________________________________________________________________________________________________
______________________CLA_______________________________________________________________________________________________
Fix file:
../Examples/CLA/logic_AND_function_use_ADC_CONV_and_GPIO_as_input/main.c

fix reason: Modify the frequency division coefficient and the conversion time calculation method in the readme.

V1.2.0:
void adc_config(void)
{
    /* reset ADC */
    adc_deinit(ADC0);
    /* ADC clock configuration */
    adc_clock_config(ADC0, ADC_CLK_ASYNC_DIV64);
    /* ADC scan mode enable */
    adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
    /* ADC data alignment configuration */
    adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
    /* ADC channel length configuration */
    adc_channel_length_config(ADC0, ADC_ROUTINE_CHANNEL, 1);
    /* ADC routine channel configuration */
    adc_routine_channel_config(ADC0, 0, ADC_CHANNEL_0, 24);
    /* ADC trigger configuration */
    adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
    /* enable ADC interface */
    adc_enable(ADC0);
    /* wait for ADC stability */
    delay_1ms(1);
    /* ADC calibration mode configuration */
    adc_calibration_mode_config(ADC0, ADC_CALIBRATION_OFFSET_MISMATCH);
    /* ADC calibration number configuration */
    adc_calibration_number(ADC0, ADC_CALIBRATION_NUM1);
    /* ADC calibration and reset calibration */
    adc_calibration_enable(ADC0);
}

V1.3.0:
void adc_config(void)
{
    /* reset ADC */
    adc_deinit(ADC0);
    /* ADC clock configuration */
    adc_clock_config(ADC0, ADC_CLK_SYNC_HCLK_DIV16);
    /* ADC scan mode enable */
    adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
    /* ADC data alignment configuration */
    adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
    /* ADC channel length configuration */
    adc_channel_length_config(ADC0, ADC_ROUTINE_CHANNEL, 1);
    /* ADC routine channel configuration */
    adc_routine_channel_config(ADC0, 0, ADC_CHANNEL_0, 0);
    /* ADC trigger configuration */
    adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
    /* enable ADC interface */
    adc_enable(ADC0);
    /* wait for ADC stability */
    delay_1ms(1);
    /* ADC calibration mode configuration */
    adc_calibration_mode_config(ADC0, ADC_CALIBRATION_OFFSET_MISMATCH);
    /* ADC calibration number configuration */
    adc_calibration_number(ADC0, ADC_CALIBRATION_NUM1);
    /* ADC calibration and reset calibration */
    adc_calibration_enable(ADC0);
}
____________________________________________________________________________________________________________________________
______________________CLA_______________________________________________________________________________________________
Fix file:
../Examples/CLA/use_CLA0_result_as_CLA1_input/main.c

fix reason: Bug Fix.

V1.2.0:
1. 
    /* PB5 outputs LOW */
    gpio_bit_reset(GPIOB, GPIO_PIN_5);
V1.3.0:
1. 
    /* PB5 outputs HIGH */
    gpio_bit_set(GPIOB, GPIO_PIN_5);
2. Add function cla0_output_gpio_config
____________________________________________________________________________________________________________________________
______________________ADC_______________________________________________________________________________________________
Fix file:
../Examples/ADC/ADC0_ADC2_temperature_Vref_Vbat/main.c

fix reason: Delete unuseful function.

V1.2.0:

V1.3.0:
    Add function adc_clock_config(ADC2, ADC_CLK_ASYNC_DIV64).
____________________________________________________________________________________________________________________________
______________________I2C_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_i2c.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_i2c.c

fix reason: Delete not support function.

V1.2.0:

V1.3.0:
    Delete function i2c_nack_disable.
____________________________________________________________________________________________________________________________
______________________SPI_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_spi.c

fix reason: Modify function.

V1.2.0:
FlagStatus spi_flag_get(uint32_t spi_periph, uint32_t flag)
{
    if(RESET != (SPI_STAT(spi_periph) & flag)) {
        return SET;
    } else {
        if(SPI1 == spi_periph) {
            /* check TXFIFO is empty or not */
            if(SPI_TXLVL_EMPTY == flag) {
                if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)) {
                    return RESET;
                } else {
                    return SET;
                }
            }
            /* check RXFIFO is empty or not */
            if(SPI_RXLVL_EMPTY == flag) {
                if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)) {
                    return RESET;
                } else {
                    return SET;
                }
            }
        }
        return RESET;
    }
}
V1.3.0:
FlagStatus spi_flag_get(uint32_t spi_periph, uint32_t flag)
{
    FlagStatus reval = RESET;

    /* check TXFIFO is empty or not */
    if(SPI_FLAG_TXLVL_EMPTY == flag) {
        if(SPI_TXLVL_EMPTY != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)) {
            reval = RESET;
        } else {
            reval = SET;
        }
    }
    /* check RXFIFO is empty or not */
    else if(SPI_FLAG_RXLVL_EMPTY == flag) {
        if(SPI_RXLVL_EMPTY != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)) {
            reval = RESET;
        } else {
            reval = SET;
        }
    } else {
        if (flag != (SPI_STAT(spi_periph) & flag)){
            reval = RESET;
        } else {
            reval = SET;
        }
    }

    return reval;
}
____________________________________________________________________________________________________________________________
______________________SPI_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_spi.h

fix reason: Delete not support function.

V1.2.0:
SPI_TXLVL_HAlF_FULL
SPI_RXLVL_HAlF_FULL
SPI_FLAG_TXLVL_HAlF_FULL
SPI_FLAG_RXLVL_HAlF_FULL

V1.3.0:
SPI_TXLVL_HALF_FULL
SPI_RXLVL_HALF_FULL
SPI_FLAG_TXLVL_HALF_FULL
SPI_FLAG_RXLVL_HALF_FULL
____________________________________________________________________________________________________________________________
______________________SPI_______________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_spi.c

fix reason: Delete not support function.

V1.2.0:
SPI_TXLVL_EMPTY_MASK
SPI_RXLVL_EMPTY_MASK

V1.3.0:
SPI_TXLVL_MASK
SPI_RXLVL_MASK
____________________________________________________________________________________________________________________________
______________________SPI_______________________________________________________________________________________________
Fix file:
../Examples/SPI/SPI_master_slave_fullduplex_dma/main.c
../Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c

fix reason: Add function.

V1.2.0:

V1.3.0:
Add the following function.
#if SPI_CRC_ENABLE
    /* configure SPI CRC function */
    spi_crc_length_set(SPI0, SPI_CRC_8BIT);
    spi_crc_length_set(SPI1, SPI_CRC_8BIT);

    spi_crc_polynomial_set(SPI0, 7);
    spi_crc_polynomial_set(SPI1, 7);
    spi_crc_on(SPI0);
    spi_crc_on(SPI1);
#endif /* enable CRC function */
____________________________________________________________________________________________________________________________
******************* V1.2.0 2025-04-11******************************************************************************************
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32G5x3/Source/system_gd32g5x3.c

fix reason: 
Add GD32G553XXX3(for GD32G553VET3, GD32G553MET3, GD32G553RET3, GD32G553CET3 and GD32G553CEU3), the maximum frequency is 170Mhz.

V1.1.0:
/* select a system clock by uncommenting the following line */
/* use IRC8M */
//#define __SYSTEM_CLOCK_IRC8M                    (uint32_t)(__IRC8M)
//#define __SYSTEM_CLOCK_48M_PLL_IRC8M           (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_IRC8M           (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_IRC8M           (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_170M_PLL_IRC8M           (uint32_t)(170000000)
//#define __SYSTEM_CLOCK_216M_PLL_IRC8M           (uint32_t)(216000000)

/* use HXTAL = 8M */
//#define __SYSTEM_CLOCK_HXTAL                    (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_HXTAL           (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_170M_PLL_HXTAL           (uint32_t)(170000000)
#define __SYSTEM_CLOCK_216M_PLL_HXTAL           (uint32_t)(216000000)

V1.2.0:
/* select a system clock by uncommenting the following line */
#if !defined(GD32G553XXX3)
//#define __SYSTEM_CLOCK_IRC8M                    (uint32_t)(__IRC8M)
//#define __SYSTEM_CLOCK_48M_PLL_IRC8M           (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_IRC8M           (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_IRC8M           (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_170M_PLL_IRC8M           (uint32_t)(170000000)
//#define __SYSTEM_CLOCK_216M_PLL_IRC8M           (uint32_t)(216000000)
#else
//#define __SYSTEM_CLOCK_IRC8M                    (uint32_t)(__IRC8M)
//#define __SYSTEM_CLOCK_48M_PLL_IRC8M           (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_IRC8M           (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_IRC8M           (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_170M_PLL_IRC8M           (uint32_t)(170000000)
#endif

/* use HXTAL = 8M */
#if !defined(GD32G553XXX3)
//#define __SYSTEM_CLOCK_HXTAL                    (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_HXTAL           (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_170M_PLL_HXTAL           (uint32_t)(170000000)
#define __SYSTEM_CLOCK_216M_PLL_HXTAL           (uint32_t)(216000000)
#else
//#define __SYSTEM_CLOCK_HXTAL                    (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_120M_PLL_HXTAL           (uint32_t)(120000000)
#define __SYSTEM_CLOCK_170M_PLL_HXTAL           (uint32_t)(170000000)
#endif
__________________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32G5x3/Include/gd32g5x3.h
../Examples/RTC/Auto_wakeup/main.c

fix reason: 
Ensure the naming is consistent with the UM.

V1.1.0:
RTC_IRQn

V1.2.0:
RTC_WKUP_IRQn
__________________________________________________________________________________________________________________________________
______________________I2C_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_i2c.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_i2c.c

fix reason: 
modify the data type of input parameter.

V1.1.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
{
    I2C_CTL1(i2c_periph) &= (uint32_t)(~I2C_CTL1_BYTENUM);
    I2C_CTL1(i2c_periph) |= (uint32_t)(byte_number << CTL1_BYTENUM_OFFSET);
}

V1.2.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)
{
    I2C_CTL1(i2c_periph) &= (uint32_t)(~I2C_CTL1_BYTENUM);
    I2C_CTL1(i2c_periph) |= (uint32_t)((uint32_t)byte_number << CTL1_BYTENUM_OFFSET);
}
__________________________________________________________________________________________________________________________________
______________________HRTIMER_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hrtimer.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hrtimer.c

fix reason: 
Bug fix. hrtimer_slavetimer_waveform_config(update_source) cross-register.

V1.1.0:
uint32_t update_source;

void hrtimer_slavetimer_waveform_config(uint32_t hrtimer_periph, uint32_t timer_id, hrtimer_timercfg_parameter_struct * timercfg)
{
    uint32_t stxctl0_reg;
    uint32_t stxfltctl_reg;
    uint32_t stxchoctl_reg;
    uint32_t stxcntrsta_reg;
    uint32_t stxactl_reg;

    /* get the value of registers */
    stxctl0_reg = HRTIMER_STXCTL0(hrtimer_periph, timer_id);
    stxfltctl_reg = HRTIMER_STXFLTCTL(hrtimer_periph, timer_id);
    stxchoctl_reg = HRTIMER_STXCHOCTL(hrtimer_periph, timer_id);
    stxactl_reg = HRTIMER_STXACTL(hrtimer_periph, timer_id);
    
    stxcntrsta_reg = HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id);

    /* set the balanced mode */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_BLNMEN);
    stxctl0_reg |= timercfg->balanced_mode;
  
    /* update event generated by reset event */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_UPRST);
    stxctl0_reg |= timercfg->reset_update;
  
    /* set the timer update source */
    if(timercfg->update_source < HRTIMER_STXUPDATETRIGGER_ST6) {
        stxctl0_reg &= ~(STX_UPDATESOURCE_MASK0_5);
        stxactl_reg &= ~(STX_UPDATESOURCE_MASK6_7);
        stxctl0_reg |= timercfg->update_source;
    }else{
        stxctl0_reg &= ~(STX_UPDATESOURCE_MASK0_5);
        stxactl_reg &= ~(STX_UPDATESOURCE_MASK6_7);
        stxactl_reg |= (timercfg->update_source & 0x7FFFFFFFU);
    }
    /* enable/disable the fault channel (at Slave_TIMER level) */
    stxfltctl_reg &= ~(STX_FAULTCH_MASK);
    stxfltctl_reg |= (timercfg->fault_enable & STX_FAULTCH_MASK);
  
    /* protect fault enable (at Slave_TIMER level) */
    stxfltctl_reg &= ~(HRTIMER_STXFLTCTL_FLTENPROT);
    stxfltctl_reg |= timercfg->fault_protect;
  
    /* enable/disable dead time insertion (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_DTEN);
    stxchoctl_reg |= timercfg->deadtime_enable;

    /* enable/disable delayed IDLE (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_DLYISCH| HRTIMER_STXCHOCTL_DLYISMEN);
    stxchoctl_reg |= timercfg->delayed_idle;
    
    /* balanced idle automatic resumption (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_BALIAR);
    stxchoctl_reg |= timercfg->balanced_idle_automatic_resume;
  
    /* configure the Slave_TIMER counter reset event in HRTIMER_STXCNTRST register */
    HRTIMER_STXCNTRST(hrtimer_periph, timer_id) = (uint32_t)(timercfg->cnt_reset);
    /* configure the Slave_TIMER counter reset event in HRTIMER_STXCNTRSTA register */
    stxcntrsta_reg &= ~0x0000007FU;
    stxcntrsta_reg |= (uint32_t)((timercfg->cnt_reset) >> 32U);
    HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id) = stxcntrsta_reg;

    HRTIMER_STXCTL0(hrtimer_periph, timer_id) = stxctl0_reg;
    HRTIMER_STXFLTCTL(hrtimer_periph, timer_id) = stxfltctl_reg;
    HRTIMER_STXCHOCTL(hrtimer_periph, timer_id) = stxchoctl_reg;
    HRTIMER_STXACTL(hrtimer_periph, timer_id) = stxactl_reg;
}

V1.2.0:
uint64_t update_source;

void hrtimer_slavetimer_waveform_config(uint32_t hrtimer_periph, uint32_t timer_id, hrtimer_timercfg_parameter_struct * timercfg)
{
    uint32_t stxctl0_reg;
    uint32_t stxfltctl_reg;
    uint32_t stxchoctl_reg;
    uint32_t stxcntrsta_reg;
    uint32_t stxactl_reg;

    /* get the value of registers */
    stxctl0_reg = HRTIMER_STXCTL0(hrtimer_periph, timer_id);
    stxfltctl_reg = HRTIMER_STXFLTCTL(hrtimer_periph, timer_id);
    stxchoctl_reg = HRTIMER_STXCHOCTL(hrtimer_periph, timer_id);
    stxactl_reg = HRTIMER_STXACTL(hrtimer_periph, timer_id);
    
    stxcntrsta_reg = HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id);

    /* set the balanced mode */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_BLNMEN);
    stxctl0_reg |= timercfg->balanced_mode;
  
    /* update event generated by reset event */
    stxctl0_reg &= ~(HRTIMER_STXCTL0_UPRST);
    stxctl0_reg |= timercfg->reset_update;
  
    /* set the timer update source in HRTIMER_STXCTL0 register */
    stxctl0_reg &= ~(STX_UPDATESOURCE_MASK0_5);    
    stxctl0_reg |= (uint32_t)(timercfg->update_source);
    /* set the timer update source in HRTIMER_STXACTL register */
    stxactl_reg &= ~(STX_UPDATESOURCE_MASK6_7);
    stxactl_reg |= (uint32_t)(timercfg->update_source >> 32);
    
    /* enable/disable the fault channel (at Slave_TIMER level) */
    stxfltctl_reg &= ~(STX_FAULTCH_MASK);
    stxfltctl_reg |= (timercfg->fault_enable & STX_FAULTCH_MASK);
  
    /* protect fault enable (at Slave_TIMER level) */
    stxfltctl_reg &= ~(HRTIMER_STXFLTCTL_FLTENPROT);
    stxfltctl_reg |= timercfg->fault_protect;
  
    /* enable/disable dead time insertion (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_DTEN);
    stxchoctl_reg |= timercfg->deadtime_enable;

    /* enable/disable delayed IDLE (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_DLYISCH| HRTIMER_STXCHOCTL_DLYISMEN);
    stxchoctl_reg |= timercfg->delayed_idle;
    
    /* balanced idle automatic resumption (at Slave_TIMER level) */
    stxchoctl_reg &= ~(HRTIMER_STXCHOCTL_BALIAR);
    stxchoctl_reg |= timercfg->balanced_idle_automatic_resume;
  
    /* configure the Slave_TIMER counter reset event in HRTIMER_STXCNTRST register */
    HRTIMER_STXCNTRST(hrtimer_periph, timer_id) = (uint32_t)(timercfg->cnt_reset);
    /* configure the Slave_TIMER counter reset event in HRTIMER_STXCNTRSTA register */
    stxcntrsta_reg &= ~0x0000007FU;
    stxcntrsta_reg |= (uint32_t)((timercfg->cnt_reset) >> 32U);
    HRTIMER_STXCNTRSTA(hrtimer_periph, timer_id) = stxcntrsta_reg;

    HRTIMER_STXCTL0(hrtimer_periph, timer_id) = stxctl0_reg;
    HRTIMER_STXFLTCTL(hrtimer_periph, timer_id) = stxfltctl_reg;
    HRTIMER_STXCHOCTL(hrtimer_periph, timer_id) = stxchoctl_reg;
    HRTIMER_STXACTL(hrtimer_periph, timer_id) = stxactl_reg;
}
__________________________________________________________________________________________________________________________________
______________________HRTIMER_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_hrtimer.c

fix reason: 
Adjust the configuration order of fault input enable bit and protect fault input configuration bit within the hrtimer_fault_config.

V1.1.0:
void hrtimer_fault_config(uint32_t hrtimer_periph, uint32_t fault_id, hrtimer_faultcfg_parameter_struct* faultcfg)
{
    uint32_t fltincfg0;
    uint32_t fltincfg1;
    uint32_t fltincfg2;
    uint32_t fltincfg3;
    uint32_t fltincfg4;
  
    fltincfg0 = HRTIMER_FLTINCFG0(hrtimer_periph);
    fltincfg1 = HRTIMER_FLTINCFG1(hrtimer_periph);
    fltincfg2 = HRTIMER_FLTINCFG2(hrtimer_periph);
    fltincfg3 = HRTIMER_FLTINCFG3(hrtimer_periph);
    fltincfg4 = HRTIMER_FLTINCFG4(hrtimer_periph);
  
    switch (fault_id)
    {
        case HRTIMER_FAULT_0:
        {
            /* configure fault input 0 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT0INP | HRTIMER_FLTINCFG0_FLT0INSRC0 | HRTIMER_FLTINCFG0_FLT0INFC | HRTIMER_FLTINCFG0_FLT0INPROT | HRTIMER_FLTINCFG0_FLT0INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT0INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG0_FLT0INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 15) & HRTIMER_FLTINCFG1_FLT0INSRC1);
            fltincfg0 |= faultcfg->polarity;
            fltincfg0 |= ((faultcfg->filter) << 3);
            fltincfg0 |= faultcfg->control;
            fltincfg0 |= faultcfg->protect;
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT0BLKEN | HRTIMER_FLTINCFG2_FLT0BLKS | HRTIMER_FLTINCFG2_FLT0CNT | HRTIMER_FLTINCFG2_FLT0RST);
            fltincfg2 |= (faultcfg->blanksenable | faultcfg->blanksource | (faultcfg->counter <<2) | faultcfg->resetmode);
        }
        break;
        case HRTIMER_FAULT_1:
        {
            /* configure fault input 1 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT1INP | HRTIMER_FLTINCFG0_FLT1INSRC0 | HRTIMER_FLTINCFG0_FLT1INFC | HRTIMER_FLTINCFG0_FLT1INPROT | HRTIMER_FLTINCFG0_FLT1INEN );
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT1INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG0_FLT1INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 16) & HRTIMER_FLTINCFG1_FLT1INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 8);
            fltincfg0 |= ((faultcfg->filter) << 11);
            fltincfg0 |= ((faultcfg->control) << 8);
            fltincfg0 |= ((faultcfg->protect) << 8);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT1BLKEN | HRTIMER_FLTINCFG2_FLT1BLKS | HRTIMER_FLTINCFG2_FLT1CNT | HRTIMER_FLTINCFG2_FLT1RST);
            fltincfg2 |= ((faultcfg->blanksenable << 8) | (faultcfg->blanksource << 8) | (faultcfg->counter << 10) | (faultcfg->resetmode << 8));
        }
        break;
        case HRTIMER_FAULT_2:
        {
            /* configure fault input 2 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT2INP | HRTIMER_FLTINCFG0_FLT2INSRC0 | HRTIMER_FLTINCFG0_FLT2INFC | HRTIMER_FLTINCFG0_FLT2INPROT | HRTIMER_FLTINCFG0_FLT2INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT2INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 18) & HRTIMER_FLTINCFG0_FLT2INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 17) & HRTIMER_FLTINCFG1_FLT2INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 16);
            fltincfg0 |= ((faultcfg->filter) << 19);
            fltincfg0 |= ((faultcfg->control) << 16);
            fltincfg0 |= ((faultcfg->protect) << 16);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT2BLKEN | HRTIMER_FLTINCFG2_FLT2BLKS | HRTIMER_FLTINCFG2_FLT2CNT | HRTIMER_FLTINCFG2_FLT2RST);
            fltincfg2 |= ((faultcfg->blanksenable << 16) | (faultcfg->blanksource << 16) | (faultcfg->counter << 18) | (faultcfg->resetmode << 16));
        }
        break;
        case HRTIMER_FAULT_3:
        {
            /* configure fault input 3 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT3INP | HRTIMER_FLTINCFG0_FLT3INSRC0 | HRTIMER_FLTINCFG0_FLT3INFC | HRTIMER_FLTINCFG0_FLT3INPROT | HRTIMER_FLTINCFG0_FLT3INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT3INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 26) & HRTIMER_FLTINCFG0_FLT3INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 18) & HRTIMER_FLTINCFG1_FLT3INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 24);
            fltincfg0 |= ((faultcfg->filter) << 27);
            fltincfg0 |= ((faultcfg->control) << 24);
            fltincfg0 |= ((faultcfg->protect) << 24);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT3BLKEN | HRTIMER_FLTINCFG2_FLT3BLKS | HRTIMER_FLTINCFG2_FLT3CNT | HRTIMER_FLTINCFG2_FLT3RST);
            fltincfg2 |= ((faultcfg->blanksenable << 24) | (faultcfg->blanksource << 24) | (faultcfg->counter << 26) | (faultcfg->resetmode << 24));
        }
        break;
        case HRTIMER_FAULT_4:
        {
            /* configure fault input 4 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT4INP | HRTIMER_FLTINCFG1_FLT4INSRC0 |  HRTIMER_FLTINCFG1_FLT4INSRC1 | HRTIMER_FLTINCFG1_FLT4INFC | HRTIMER_FLTINCFG1_FLT4INPROT | HRTIMER_FLTINCFG1_FLT4INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG1_FLT4INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 19) & HRTIMER_FLTINCFG1_FLT4INSRC1);
            fltincfg1 |= faultcfg->polarity;
            fltincfg1 |= ((faultcfg->filter) << 3);
            fltincfg1 |= (faultcfg->control);
            fltincfg1 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT4BLKEN | HRTIMER_FLTINCFG3_FLT4BLKS | HRTIMER_FLTINCFG3_FLT4CNT | HRTIMER_FLTINCFG3_FLT4RST);
            fltincfg3 |= (faultcfg->blanksenable | faultcfg->blanksource | (faultcfg->counter << 2) | faultcfg->resetmode);
        }
        break;
        case HRTIMER_FAULT_5:
        {
            /* configure fault input 5 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT5INP | HRTIMER_FLTINCFG1_FLT5INSRC0 | HRTIMER_FLTINCFG1_FLT5INSRC1 | HRTIMER_FLTINCFG1_FLT5INFC | HRTIMER_FLTINCFG1_FLT5INPROT | HRTIMER_FLTINCFG1_FLT5INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG1_FLT5INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 20) & HRTIMER_FLTINCFG1_FLT5INSRC1);
            fltincfg1 |= (faultcfg->polarity << 8);
            fltincfg1 |= ((faultcfg->filter) << 11);
            fltincfg1 |= ((faultcfg->control) << 8);
            fltincfg1 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT5BLKEN | HRTIMER_FLTINCFG3_FLT5BLKS | HRTIMER_FLTINCFG3_FLT5CNT | HRTIMER_FLTINCFG3_FLT5RST);
            fltincfg3 |= ((faultcfg->blanksenable << 8) | (faultcfg->blanksource << 8) | (faultcfg->counter << 10) | (faultcfg->resetmode << 8));
        }
        break;
        case HRTIMER_FAULT_6:
        {
            /* configure fault input 6 */
            fltincfg4 &= ~( HRTIMER_FLTINCFG4_FLT6INP | HRTIMER_FLTINCFG4_FLT6INSRC0 | HRTIMER_FLTINCFG4_FLT6INFC | HRTIMER_FLTINCFG4_FLT6INPROT | HRTIMER_FLTINCFG4_FLT6INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT6INSRC1);
            fltincfg4 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG4_FLT6INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 21) & HRTIMER_FLTINCFG1_FLT6INSRC1);
            fltincfg4 |= faultcfg->polarity;
            fltincfg4 |= ((faultcfg->filter) << 3);
            fltincfg4 |= faultcfg->control;
            fltincfg4 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT6BLKEN | HRTIMER_FLTINCFG3_FLT6BLKS | HRTIMER_FLTINCFG3_FLT6CNT | HRTIMER_FLTINCFG3_FLT6RST);
            fltincfg3 |= ((faultcfg->blanksenable << 16) | (faultcfg->blanksource << 16) | (faultcfg->counter << 18) | (faultcfg->resetmode << 16));
        }
        break;
        case HRTIMER_FAULT_7:
        {
            /* configure fault input 7 */
            fltincfg4 &= ~( HRTIMER_FLTINCFG4_FLT7INP | HRTIMER_FLTINCFG4_FLT7INSRC0 | HRTIMER_FLTINCFG4_FLT7INFC | HRTIMER_FLTINCFG4_FLT7INPROT | HRTIMER_FLTINCFG4_FLT7INEN );
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT7INSRC1);
            fltincfg4 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG4_FLT7INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 22) & HRTIMER_FLTINCFG1_FLT7INSRC1);
            fltincfg4 |= ((faultcfg->polarity) << 8);
            fltincfg4 |= ((faultcfg->filter) << 11);
            fltincfg4 |= ((faultcfg->control) << 8);
            fltincfg4 |= ((faultcfg->protect) << 8);
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT7BLKEN | HRTIMER_FLTINCFG3_FLT7BLKS | HRTIMER_FLTINCFG3_FLT7CNT | HRTIMER_FLTINCFG3_FLT7RST);
            fltincfg3 |= ((faultcfg->blanksenable << 24) | (faultcfg->blanksource << 24) | (faultcfg->counter << 26) | (faultcfg->resetmode << 24));
        }
        break;
        default:
        break;
    }
    
    HRTIMER_FLTINCFG2(hrtimer_periph) = fltincfg2;
    HRTIMER_FLTINCFG3(hrtimer_periph) = fltincfg3;
    HRTIMER_FLTINCFG0(hrtimer_periph) = fltincfg0;
    HRTIMER_FLTINCFG1(hrtimer_periph) = fltincfg1;
    HRTIMER_FLTINCFG4(hrtimer_periph) = fltincfg4;
}

V1.2.0:
void hrtimer_fault_config(uint32_t hrtimer_periph, uint32_t fault_id, hrtimer_faultcfg_parameter_struct* faultcfg)
{
    uint32_t fltincfg0;
    uint32_t fltincfg1;
    uint32_t fltincfg2;
    uint32_t fltincfg3;
    uint32_t fltincfg4;
  
    fltincfg0 = HRTIMER_FLTINCFG0(hrtimer_periph);
    fltincfg1 = HRTIMER_FLTINCFG1(hrtimer_periph);
    fltincfg2 = HRTIMER_FLTINCFG2(hrtimer_periph);
    fltincfg3 = HRTIMER_FLTINCFG3(hrtimer_periph);
    fltincfg4 = HRTIMER_FLTINCFG4(hrtimer_periph);
  
    switch (fault_id)
    {
        case HRTIMER_FAULT_0:
        {
            /* configure fault input 0 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT0INP | HRTIMER_FLTINCFG0_FLT0INSRC0 | HRTIMER_FLTINCFG0_FLT0INFC | HRTIMER_FLTINCFG0_FLT0INPROT | HRTIMER_FLTINCFG0_FLT0INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT0INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG0_FLT0INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 15) & HRTIMER_FLTINCFG1_FLT0INSRC1);
            fltincfg0 |= faultcfg->polarity;
            fltincfg0 |= ((faultcfg->filter) << 3);
            fltincfg0 |= faultcfg->control;
            fltincfg0 |= faultcfg->protect;
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT0BLKEN | HRTIMER_FLTINCFG2_FLT0BLKS | HRTIMER_FLTINCFG2_FLT0CNT | HRTIMER_FLTINCFG2_FLT0RST);
            fltincfg2 |= (faultcfg->blanksenable | faultcfg->blanksource | (faultcfg->counter <<2) | faultcfg->resetmode);
        }
        break;
        case HRTIMER_FAULT_1:
        {
            /* configure fault input 1 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT1INP | HRTIMER_FLTINCFG0_FLT1INSRC0 | HRTIMER_FLTINCFG0_FLT1INFC | HRTIMER_FLTINCFG0_FLT1INPROT | HRTIMER_FLTINCFG0_FLT1INEN );
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT1INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG0_FLT1INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 16) & HRTIMER_FLTINCFG1_FLT1INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 8);
            fltincfg0 |= ((faultcfg->filter) << 11);
            fltincfg0 |= ((faultcfg->control) << 8);
            fltincfg0 |= ((faultcfg->protect) << 8);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT1BLKEN | HRTIMER_FLTINCFG2_FLT1BLKS | HRTIMER_FLTINCFG2_FLT1CNT | HRTIMER_FLTINCFG2_FLT1RST);
            fltincfg2 |= ((faultcfg->blanksenable << 8) | (faultcfg->blanksource << 8) | (faultcfg->counter << 10) | (faultcfg->resetmode << 8));
        }
        break;
        case HRTIMER_FAULT_2:
        {
            /* configure fault input 2 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT2INP | HRTIMER_FLTINCFG0_FLT2INSRC0 | HRTIMER_FLTINCFG0_FLT2INFC | HRTIMER_FLTINCFG0_FLT2INPROT | HRTIMER_FLTINCFG0_FLT2INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT2INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 18) & HRTIMER_FLTINCFG0_FLT2INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 17) & HRTIMER_FLTINCFG1_FLT2INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 16);
            fltincfg0 |= ((faultcfg->filter) << 19);
            fltincfg0 |= ((faultcfg->control) << 16);
            fltincfg0 |= ((faultcfg->protect) << 16);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT2BLKEN | HRTIMER_FLTINCFG2_FLT2BLKS | HRTIMER_FLTINCFG2_FLT2CNT | HRTIMER_FLTINCFG2_FLT2RST);
            fltincfg2 |= ((faultcfg->blanksenable << 16) | (faultcfg->blanksource << 16) | (faultcfg->counter << 18) | (faultcfg->resetmode << 16));
        }
        break;
        case HRTIMER_FAULT_3:
        {
            /* configure fault input 3 */
            fltincfg0 &= ~( HRTIMER_FLTINCFG0_FLT3INP | HRTIMER_FLTINCFG0_FLT3INSRC0 | HRTIMER_FLTINCFG0_FLT3INFC | HRTIMER_FLTINCFG0_FLT3INPROT | HRTIMER_FLTINCFG0_FLT3INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT3INSRC1);
            fltincfg0 |= (((faultcfg->source & 0x00000001U) << 26) & HRTIMER_FLTINCFG0_FLT3INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 18) & HRTIMER_FLTINCFG1_FLT3INSRC1);
            fltincfg0 |= ((faultcfg->polarity) << 24);
            fltincfg0 |= ((faultcfg->filter) << 27);
            fltincfg0 |= ((faultcfg->control) << 24);
            fltincfg0 |= ((faultcfg->protect) << 24);
            
            fltincfg2 &= ~(HRTIMER_FLTINCFG2_FLT3BLKEN | HRTIMER_FLTINCFG2_FLT3BLKS | HRTIMER_FLTINCFG2_FLT3CNT | HRTIMER_FLTINCFG2_FLT3RST);
            fltincfg2 |= ((faultcfg->blanksenable << 24) | (faultcfg->blanksource << 24) | (faultcfg->counter << 26) | (faultcfg->resetmode << 24));
        }
        break;
        case HRTIMER_FAULT_4:
        {
            /* configure fault input 4 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT4INP | HRTIMER_FLTINCFG1_FLT4INSRC0 |  HRTIMER_FLTINCFG1_FLT4INSRC1 | HRTIMER_FLTINCFG1_FLT4INFC | HRTIMER_FLTINCFG1_FLT4INPROT | HRTIMER_FLTINCFG1_FLT4INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG1_FLT4INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 19) & HRTIMER_FLTINCFG1_FLT4INSRC1);
            fltincfg1 |= faultcfg->polarity;
            fltincfg1 |= ((faultcfg->filter) << 3);
            fltincfg1 |= (faultcfg->control);
            fltincfg1 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT4BLKEN | HRTIMER_FLTINCFG3_FLT4BLKS | HRTIMER_FLTINCFG3_FLT4CNT | HRTIMER_FLTINCFG3_FLT4RST);
            fltincfg3 |= (faultcfg->blanksenable | faultcfg->blanksource | (faultcfg->counter << 2) | faultcfg->resetmode);
        }
        break;
        case HRTIMER_FAULT_5:
        {
            /* configure fault input 5 */
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT5INP | HRTIMER_FLTINCFG1_FLT5INSRC0 | HRTIMER_FLTINCFG1_FLT5INSRC1 | HRTIMER_FLTINCFG1_FLT5INFC | HRTIMER_FLTINCFG1_FLT5INPROT | HRTIMER_FLTINCFG1_FLT5INEN);
            fltincfg1 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG1_FLT5INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 20) & HRTIMER_FLTINCFG1_FLT5INSRC1);
            fltincfg1 |= (faultcfg->polarity << 8);
            fltincfg1 |= ((faultcfg->filter) << 11);
            fltincfg1 |= ((faultcfg->control) << 8);
            fltincfg1 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT5BLKEN | HRTIMER_FLTINCFG3_FLT5BLKS | HRTIMER_FLTINCFG3_FLT5CNT | HRTIMER_FLTINCFG3_FLT5RST);
            fltincfg3 |= ((faultcfg->blanksenable << 8) | (faultcfg->blanksource << 8) | (faultcfg->counter << 10) | (faultcfg->resetmode << 8));
        }
        break;
        case HRTIMER_FAULT_6:
        {
            /* configure fault input 6 */
            fltincfg4 &= ~( HRTIMER_FLTINCFG4_FLT6INP | HRTIMER_FLTINCFG4_FLT6INSRC0 | HRTIMER_FLTINCFG4_FLT6INFC | HRTIMER_FLTINCFG4_FLT6INPROT | HRTIMER_FLTINCFG4_FLT6INEN);
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT6INSRC1);
            fltincfg4 |= (((faultcfg->source & 0x00000001U) << 2) & HRTIMER_FLTINCFG4_FLT6INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 21) & HRTIMER_FLTINCFG1_FLT6INSRC1);
            fltincfg4 |= faultcfg->polarity;
            fltincfg4 |= ((faultcfg->filter) << 3);
            fltincfg4 |= faultcfg->control;
            fltincfg4 |= faultcfg->protect;
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT6BLKEN | HRTIMER_FLTINCFG3_FLT6BLKS | HRTIMER_FLTINCFG3_FLT6CNT | HRTIMER_FLTINCFG3_FLT6RST);
            fltincfg3 |= ((faultcfg->blanksenable << 16) | (faultcfg->blanksource << 16) | (faultcfg->counter << 18) | (faultcfg->resetmode << 16));
        }
        break;
        case HRTIMER_FAULT_7:
        {
            /* configure fault input 7 */
            fltincfg4 &= ~( HRTIMER_FLTINCFG4_FLT7INP | HRTIMER_FLTINCFG4_FLT7INSRC0 | HRTIMER_FLTINCFG4_FLT7INFC | HRTIMER_FLTINCFG4_FLT7INPROT | HRTIMER_FLTINCFG4_FLT7INEN );
            fltincfg1 &= ~( HRTIMER_FLTINCFG1_FLT7INSRC1);
            fltincfg4 |= (((faultcfg->source & 0x00000001U) << 10) & HRTIMER_FLTINCFG4_FLT7INSRC0);
            fltincfg1 |= (((faultcfg->source & 0x00000002U) << 22) & HRTIMER_FLTINCFG1_FLT7INSRC1);
            fltincfg4 |= ((faultcfg->polarity) << 8);
            fltincfg4 |= ((faultcfg->filter) << 11);
            fltincfg4 |= ((faultcfg->control) << 8);
            fltincfg4 |= ((faultcfg->protect) << 8);
            
            fltincfg3 &= ~(HRTIMER_FLTINCFG3_FLT7BLKEN | HRTIMER_FLTINCFG3_FLT7BLKS | HRTIMER_FLTINCFG3_FLT7CNT | HRTIMER_FLTINCFG3_FLT7RST);
            fltincfg3 |= ((faultcfg->blanksenable << 24) | (faultcfg->blanksource << 24) | (faultcfg->counter << 26) | (faultcfg->resetmode << 24));
        }
        break;
        default:
        break;
    }
    
    /* configure fault input configuration register except input enable bit and protect fault input configuration bit */
    HRTIMER_FLTINCFG2(hrtimer_periph) = fltincfg2;
    HRTIMER_FLTINCFG3(hrtimer_periph) = fltincfg3;
    HRTIMER_FLTINCFG0(hrtimer_periph) = (fltincfg0 & (~0x81818181U));
    HRTIMER_FLTINCFG1(hrtimer_periph) = (fltincfg1 & (~0x00008181U));
    HRTIMER_FLTINCFG4(hrtimer_periph) = (fltincfg4 & (~0x00008181U));
    
    /* configure fault input configuration register input enable bit */
    HRTIMER_FLTINCFG0(hrtimer_periph) |= (fltincfg0 & (0x01010101U));
    HRTIMER_FLTINCFG1(hrtimer_periph) |= (fltincfg1 & (0x00000101U));
    HRTIMER_FLTINCFG4(hrtimer_periph) |= (fltincfg4 & (0x00000101U));
    
    /* configure fault input configuration register protect fault input configuration bit */
    HRTIMER_FLTINCFG0(hrtimer_periph) |= (fltincfg0 & (0x80808080U)); 
    HRTIMER_FLTINCFG1(hrtimer_periph) |= (fltincfg1 & (0x00008080U));
    HRTIMER_FLTINCFG4(hrtimer_periph) |= (fltincfg4 & (0x00008080U));
}
__________________________________________________________________________________________________________________________________
______________________FMC_________________________________________________________________________________________________
Fix file:
../Examples/FMC/Erase_Program/main.c

fix reason: 
Modify to support single and dual bank.

V1.1.0:
uint32_t get_bank_number(uint32_t address)
{
    uint32_t base0_address;
    
    if(OB_DUAL_BANK_MODE == (FMC_OBCTL & FMC_OBCTL_DBS)){
        return FMC_BANK0;
    }else{
        base0_address = fmc_bank0_base_address_get();    
        if((address >= base0_address) && (address < (base0_address + MAIN_FLASH_BANK_SIZE))){
            return FMC_BANK0;
        }else{
            return FMC_BANK1;
        }   
    }
}

V1.2.0:
uint32_t get_bank_number(uint32_t address)
{
    uint32_t base0_address;
    
    if(OB_DUAL_BANK_MODE != (FMC_OBCTL & FMC_OBCTL_DBS)){
        return FMC_BANK0;
    }else{
        base0_address = fmc_bank0_base_address_get();    
        if((address >= base0_address) && (address < (base0_address + MAIN_FLASH_BANK_SIZE))){
            return FMC_BANK0;
        }else{
            return FMC_BANK1;
        }   
    }
}
__________________________________________________________________________________________________________________________________
______________________FMC_________________________________________________________________________________________________
Fix file:
../Examples/FMC/Erase_Program/main.c

fix reason: 
Remove the FMC_FLAG_ENDF flag bit, it is only set when the interrupt is enabled.

V1.1.0:
    fmc_flag_clear(FMC_FLAG_ENDF | FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_OPRERR | FMC_FLAG_PGSERR | FMC_FLAG_PGMERR | FMC_FLAG_PGAERR);

V1.2.0:
    fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_OPRERR | FMC_FLAG_PGSERR | FMC_FLAG_PGMERR | FMC_FLAG_PGAERR);
__________________________________________________________________________________________________________________________________
______________________FMC_________________________________________________________________________________________________
Fix file:
../Examples/FMC/Erase_Program/main.c

fix reason: 
Bug Fix, when calculating the bank size, it should be multiplied by 0x400.

V1.1.0:
uint32_t get_bank_number(uint32_t address)
{
    uint32_t base0_address;
    
    if(OB_DUAL_BANK_MODE != (FMC_OBCTL & FMC_OBCTL_DBS)){
        return FMC_BANK0;
    }else{
        base0_address = fmc_bank0_base_address_get();    
        if((address >= base0_address) && (address < (base0_address + MAIN_FLASH_BANK_SIZE))){
            return FMC_BANK0;
        }else{
            return FMC_BANK1;
        }   
    }
}

V1.2.0:
uint32_t get_bank_number(uint32_t address)
{
    uint32_t base0_address;
    
    if(OB_DUAL_BANK_MODE != (FMC_OBCTL & FMC_OBCTL_DBS)){
        return FMC_BANK0;
    }else{
        base0_address = fmc_bank0_base_address_get();    
        if((address >= base0_address) && (address < (base0_address + MAIN_FLASH_BANK_SIZE * 0x400U))){
            return FMC_BANK0;
        }else{
            return FMC_BANK1;
        }   
    }
}
__________________________________________________________________________________________________________________________________
______________________RCU_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rcu.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rcu.c

fix reason: 
Delete the LSE driver mode configuration to 00.

V1.1.0:
#define BDCTL_LXTALDRI(regval)       (BITS(3,4) & ((uint32_t)(regval) << 3U))
#define RCU_LXTAL_LOWDRI             BDCTL_LXTALDRI(0)                               /*!< lower driving capability */
#define RCU_LXTAL_MED_LOWDRI         BDCTL_LXTALDRI(1)                               /*!< medium low driving capability */
#define RCU_LXTAL_MED_HIGHDRI        BDCTL_LXTALDRI(2)                               /*!< medium high driving capability */
#define RCU_LXTAL_HIGHDRI            BDCTL_LXTALDRI(3)                               /*!< higher driving capability */

V1.2.0:
#define BDCTL_LXTALDRI(regval)       (BITS(3,4) & ((uint32_t)(regval) << 3U))
#define RCU_LXTAL_LOWDRI             BDCTL_LXTALDRI(1)                               /*!< low driving capability */
#define RCU_LXTAL_MEDDRI             BDCTL_LXTALDRI(2)                               /*!< medium driving capability */
#define RCU_LXTAL_HIGHDRI            BDCTL_LXTALDRI(3)                               /*!< high driving capability */
__________________________________________________________________________________________________________________________________
______________________RTC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_rtc.c

fix reason: 
Bug fix, subsecond registers can be manipulated without entering init mode.

V1.1.0:
void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    /* 2nd: enter init mode */
    if(ERROR != (rtc_init_mode_enter())) {
        if(RTC_ALARM0 == rtc_alarm) {
            RTC_ALRM0SS = mask_subsecond | subsecond;
        } else {
            RTC_ALRM1SS = mask_subsecond | subsecond;
        }
    }

V1.2.0:
void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    if(RTC_ALARM0 == rtc_alarm) {
        RTC_ALRM0SS = mask_subsecond | subsecond;
    } else {
        RTC_ALRM1SS = mask_subsecond | subsecond;
    }
__________________________________________________________________________________________________________________________________
______________________CMP_________________________________________________________________________________________________
Fix file:
../Examples/CMP/Timer0_CH0IC/main.c

fix reason: 
Modify channel input capture filter configuration.

V1.1.0:
timer_icinitpara.icfilter    = 0x15;

V1.2.0:
timer_icinitpara.icfilter    = 0x05;
__________________________________________________________________________________________________________________________________

******************* V1.1.0 2025-02-10******************************************************************************************
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32G5x3/Include/gd32g5x3.h

fix reason: 
Bug fix, delete IRC48M configuration and change IRC40K to IRC32K.

V1.0.0:
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined  (IRC48M_VALUE) 
#define IRC48M_VALUE  ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */

/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined  (IRC40K_VALUE) 
#define IRC40K_VALUE  ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */

V1.1.0:
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
#if !defined  (IRC32K_VALUE) 
#define IRC32K_VALUE  ((uint32_t)32000)
#endif /* internal 32KHz RC oscillator value */
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_syscfg.h

fix reason: 
Bug fix, change IRC40K to IRC32K.

V1.0.0:
TIMER4_CI0_INPUT_IRC40K
TIMER15_CI0_INPUT_IRC40K
TIMER16_CI0_INPUT_IRC40K
V1.1.0:
TIMER4_CI0_INPUT_IRC32K
TIMER15_CI0_INPUT_IRC32K
TIMER16_CI0_INPUT_IRC32K
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32G5x3/Source/system_gd32g5x3.c

fix reason: 
Bug fix, switch frequency, fix partial code addition.

V1.0.0:

V1.1.0:
Modify the frequency switch method.
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_syscfg.c

fix reason: 
Bug fix, syscfg_i2c_fast_mode_plus_enable and syscfg_i2c_fast_mode_plus_disable.

V1.0.0:
void syscfg_i2c_fast_mode_plus_enable(uint32_t i2c_fmp_enable)
{
    SYSCFG_CFG0 |= i2c_fmp_enable;
}
void syscfg_i2c_fast_mode_plus_disable(uint32_t i2c_fmp_disable)
{
    SYSCFG_CFG0 &= (uint32_t)(~i2c_fmp_disable);
}
V1.1.0:
void syscfg_i2c_fast_mode_plus_enable(uint32_t i2c_fmp_enable)
{
    SYSCFG_CFG1 |= i2c_fmp_enable;
}
void syscfg_i2c_fast_mode_plus_disable(uint32_t i2c_fmp_disable)
{
    SYSCFG_CFG1 &= (uint32_t)(~i2c_fmp_disable);
}
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32G5x3/Include/gd32g5x3.h

fix reason: 
Bug fix, change the irq RCU_CTC_IRQn to RCU_IRQn.

V1.0.0:
RCU_CTC_IRQn                 = 5,      /*!< RCU and CTC interrupt                                                                   */

V1.1.0:
RCU_IRQn                     = 5,      /*!< RCU interrupt                                                                   */
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_misc.c
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.h
../Utilities/gd32g553q_eval.c

fix reason: 
modify the type of nvic_irq of nvic_irq_enable and nvic_irq_disable from uint8_t to IRQn_Type.

V1.0.0:
for example：
/* enable NVIC request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC request */
void nvic_irq_disable(uint8_t nvic_irq);

V1.1.0:
for example：
/* enable NVIC request */
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC request */
void nvic_irq_disable(IRQn_Type nvic_irq);
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Template/gd32g5x3_it.c

fix reason: 
Add Function led_spark().

V1.0.0:
void SysTick_Handler(void)
{
    delay_decrement();
}
V1.1.0:
void SysTick_Handler(void)
{
    led_spark();
    delay_decrement();
}
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Examples/CORTEX_M/MPU_memory_management_fault

fix reason: 
Add example.

V1.0.0:

V1.1.0:
Add example MPU_memory_management_fault.
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.h

fix reason: 
Added MPU related function.

V1.0.0:

V1.1.0:
Add

#if (__MPU_PRESENT == 1U)

/* MPU region init parameter struct definitions */
typedef struct
{
    uint8_t  region_number;           /*!< region number */
    uint32_t region_base_address;     /*!< region base address */
    uint32_t region_limit_address;    /*!< region limit address */
    uint8_t  access_permission;       /*!< access permissions(AP) field */
    uint8_t  instruction_exec;        /*!< execute never */
    uint8_t  shareability;            /*!< defines the shareability for Normal memory */
    uint8_t  attribute_index;         /*!< attribute index */
}mpu_region_init_struct;

typedef struct
{
  uint8_t attribute_number;           /*!< attribute number */
  uint8_t memory_type;                /*!< memory type */
  uint8_t outer_attributes;           /*!< outer memory attributes */
  uint8_t inner_attributes;           /*!< inner memory attributes */
} mpu_attribute_init_struct;

#endif /* __MPU_PRESENT */
#if (__MPU_PRESENT == 1U)

#define MPU_REGION_NUMBER0              ((uint8_t)0x00U)          /*!< MPU region number 0 */
#define MPU_REGION_NUMBER1              ((uint8_t)0x01U)          /*!< MPU region number 1 */
#define MPU_REGION_NUMBER2              ((uint8_t)0x02U)          /*!< MPU region number 2 */
#define MPU_REGION_NUMBER3              ((uint8_t)0x03U)          /*!< MPU region number 3 */
#define MPU_REGION_NUMBER4              ((uint8_t)0x04U)          /*!< MPU region number 4 */
#define MPU_REGION_NUMBER5              ((uint8_t)0x05U)          /*!< MPU region number 5 */
#define MPU_REGION_NUMBER6              ((uint8_t)0x06U)          /*!< MPU region number 6 */
#define MPU_REGION_NUMBER7              ((uint8_t)0x07U)          /*!< MPU region number 7 */

#define MPU_REGION_PRIVILEGED_RW        ((uint8_t)0x00U)          /*!< MPU region read/write by privileged code only */
#define MPU_REGION_ALL_RW               ((uint8_t)0x01U)          /*!< MPU region read/write by any privilege level  */
#define MPU_REGION_PRIVILEGED_RO        ((uint8_t)0x02U)          /*!< MPU region read-only by privileged code only  */
#define MPU_REGION_ALL_RO               ((uint8_t)0x03U)          /*!< MPU region read-only by any privilege level   */

#define MPU_ACCESS_NOT_SHAREABLE        ((uint8_t)0x00U)          /*!< MPU access shareable */
#define MPU_ACCESS_OUTER_SHAREABLE      ((uint8_t)0x01U)          /*!< MPU region outer shareable */
#define MPU_ACCESS_INNER_SHAREABLE      ((uint8_t)0x03U)          /*!< MPU region inner shareable */

#define MPU_INSTRUCTION_EXEC_PERMIT     ((uint8_t)0x00U)          /*!< execution of an instruction fetched from this region permitted */
#define MPU_INSTRUCTION_EXEC_NOT_PERMIT ((uint8_t)0x01U)          /*!< execution of an instruction fetched from this region not permitted */

#define MPU_MODE_HFNMI_PRIVDEF_NONE     ((uint32_t)0x00000000U)   /*!< HFNMIENA and PRIVDEFENA are 0 */
#define MPU_MODE_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk     /*!< use the MPU for memory accesses by HardFault and NMI handlers only */
#define MPU_MODE_PRIV_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk   /*!< enables the default memory map as a background region for privileged access only */
#define MPU_MODE_HFNMI_PRIVDEF          ((uint32_t)MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< HFNMIENA and PRIVDEFENA are 1 */

#define MPU_ATTRIBUTE_NUMBER0           ((uint8_t)0x00U)          /*!< MPU attribute number 0 */
#define MPU_ATTRIBUTE_NUMBER1           ((uint8_t)0x01U)          /*!< MPU attribute number 1 */
#define MPU_ATTRIBUTE_NUMBER2           ((uint8_t)0x02U)          /*!< MPU attribute number 2 */
#define MPU_ATTRIBUTE_NUMBER3           ((uint8_t)0x03U)          /*!< MPU attribute number 3 */
#define MPU_ATTRIBUTE_NUMBER4           ((uint8_t)0x04U)          /*!< MPU attribute number 4 */
#define MPU_ATTRIBUTE_NUMBER5           ((uint8_t)0x05U)          /*!< MPU attribute number 5 */
#define MPU_ATTRIBUTE_NUMBER6           ((uint8_t)0x06U)          /*!< MPU attribute number 6 */
#define MPU_ATTRIBUTE_NUMBER7           ((uint8_t)0x07U)          /*!< MPU attribute number 7 */

#define MPU_MEMORY_DEVICE               ((uint8_t)0x00U)          /*!< MPU device memory */
#define MPU_MEMORY_NORMAL               ((uint8_t)0x01U)          /*!< MPU normal memory */

#define MPU_DEVICE_nGnRnE               ((uint8_t)0x00U)          /*!< Device, noGather, noReorder, noEarly acknowledge */
#define MPU_DEVICE_nGnRE                ((uint8_t)0x04U)          /*!< Device, noGather, noReorder, Early acknowledge*/
#define MPU_DEVICE_nGRE                 ((uint8_t)0x08U)          /*!< Device, noGather, Reorder, Early acknowledge */
#define MPU_DEVICE_GRE                  ((uint8_t)0x0CU)          /*!< Device, Gather, Reorder, Early acknowledge */

#define MPU_OUTER_DEVICE                       ((uint8_t)0x00U)        /*!< Device memory */
#define MPU_NORMAL_OUTER_WT_TRAN_W_ALLOC       ((uint8_t)0x10U)        /*!< Normal memory, Outer write-through transient, write with allocate */
#define MPU_NORMAL_OUTER_WT_TRAN_R_ALLOC       ((uint8_t)0x20U)        /*!< Normal memory, Outer write-through transient, read with allocate */
#define MPU_NORMAL_OUTER_WT_TRAN_RW_ALLOC      ((uint8_t)0x30U)        /*!< Normal memory, Outer write-through transient, read and write with allocate */
#define MPU_NORMAL_OUTER_NON_CACHEABLE         ((uint8_t)0x40U)        /*!< Normal memory, Outer non-cacheable */
#define MPU_NORMAL_OUTER_WB_TRAN_W_ALLOC       ((uint8_t)0x50U)        /*!< Normal memory, Outer write-back transient, write with allocate */
#define MPU_NORMAL_OUTER_WB_TRAN_R_ALLOC       ((uint8_t)0x60U)        /*!< Normal memory, Outer write-back transient, read with allocate */
#define MPU_NORMAL_OUTER_WB_TRAN_RW_ALLOC      ((uint8_t)0x70U)        /*!< Normal memory, Outer write-back transient, read and write with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_NO_ALLOC  ((uint8_t)0x80U)        /*!< Normal memory, Outer write-through non-transient, no allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_W_ALLOC   ((uint8_t)0x90U)        /*!< Normal memory, Outer write-back non-transient, write with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_R_ALLOC   ((uint8_t)0xA0U)        /*!< Normal memory, Outer write-back non-transient, read with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_RW_ALLOC  ((uint8_t)0xB0U)        /*!< Normal memory, Outer write-back non-transient, read and write with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_NO_ALLOC  ((uint8_t)0xC0U)        /*!< Normal memory, Outer write-back non-transient, no allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_W_ALLOC   ((uint8_t)0xD0U)        /*!< Normal memory, Outer write-back non-transient, write with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_R_ALLOC   ((uint8_t)0xE0U)        /*!< Normal memory, Outer write-back non-transient, read with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_RW_ALLOC  ((uint8_t)0xF0U)        /*!< Normal memory, Outer write-back non-transient, read and write with allocate */

#define MPU_NORMAL_INNER_WT_TRAN_W_ALLOC       ((uint8_t)0x01U)        /*!< Normal memory, Inner write-through transient, write with allocate */
#define MPU_NORMAL_INNER_WT_TRAN_R_ALLOC       ((uint8_t)0x02U)        /*!< Normal memory, Inner write-through transient, read with allocate */
#define MPU_NORMAL_INNER_WT_TRAN_RW_ALLOC      ((uint8_t)0x03U)        /*!< Normal memory, Inner write-through transient, read and write with allocate */
#define MPU_NORMAL_INNER_NON_CACHEABLE         ((uint8_t)0x04U)        /*!< Normal memory, Inner non-cacheable */
#define MPU_NORMAL_INNER_WB_TRAN_W_ALLOC       ((uint8_t)0x05U)        /*!< Normal memory, Inner write-back transient, write with allocate */
#define MPU_NORMAL_INNER_WB_TRAN_R_ALLOC       ((uint8_t)0x06U)        /*!< Normal memory, Inner write-back transient, read with allocate */
#define MPU_NORMAL_INNER_WB_TRAN_RW_ALLOC      ((uint8_t)0x07U)        /*!< Normal memory, Inner write-back transient, read and write with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_NO_ALLOC  ((uint8_t)0x08U)        /*!< Normal memory, Inner write-through non-transient */
#define MPU_NORMAL_INNER_WT_NON_TRAN_W_ALLOC   ((uint8_t)0x09U)        /*!< Normal memory, Inner write-back non-transient, write with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_R_ALLOC   ((uint8_t)0x0AU)        /*!< Normal memory, Inner write-back non-transient, read with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_RW_ALLOC  ((uint8_t)0x0BU)        /*!< Normal memory, Inner write-back non-transient, read and write with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_NO_ALLOC  ((uint8_t)0x0CU)        /*!< Normal memory, Inner write-back non-transient, no allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_W_ALLOC   ((uint8_t)0x0DU)        /*!< Normal memory, Inner write-back non-transient, write with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_R_ALLOC   ((uint8_t)0x0EU)        /*!< Normal memory, Inner write-back non-transient, read with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_RW_ALLOC  ((uint8_t)0x0FU)        /*!< Normal memory, Inner write-back non-transient, read and write with allocate */

#endif /* __MPU_PRESENT */

#if (__MPU_PRESENT == 1U)
/* enable the MPU */
void mpu_enable(uint32_t MPU_Control);
/* disable the MPU */
void mpu_disable(void);
/* initialize mpu_region_init_struct with the default values */
void mpu_region_struct_para_init(mpu_region_init_struct *region_init_struct);
/* initialize mpu_attribute_init_struct with the default values */
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct);
/* configure the MPU region */
void mpu_region_config(mpu_region_init_struct *region_init_struct);
/* configure the MPU attribute */
void mpu_attribute_config(mpu_attribute_init_struct *attribute_init_struct);
/* enable the MPU region */
void mpu_region_enable(void);
#endif /* __MPU_PRESENT */
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_misc.c

fix reason: 
Added MPU related function.

V1.0.0:

V1.1.0:
Add

#if (__MPU_PRESENT == 1U)

/*!
    \brief      enable the MPU
    \param[in]  MPU_Control: select a different MPU mode
      \arg        MPU_MODE_HFNMI_PRIVDEF_NONE: HFNMIENA and PRIVDEFENA are 0
      \arg        MPU_MODE_HARDFAULT_NMI: use the MPU for memory accesses by HardFault and NMI handlers only
      \arg        MPU_MODE_PRIV_DEFAULT: enables the default memory map as a background region for privileged access only
      \arg        MPU_MODE_HFNMI_PRIVDEF: HFNMIENA and PRIVDEFENA are 1
    \param[out] none
    \retval     none
*/
void mpu_enable(uint32_t MPU_Control)
{
    __DMB();
    /* enable the MPU */
    MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
    __DSB();
    __ISB();
}

/*!
    \brief      disable the MPU
    \param[in]  none
    \param[out] none
    \retval     none
*/
void mpu_disable(void)
{
    __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
    SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
    /* disable the MPU */
    MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
    __DSB();
    __ISB();
}

/*!
    \brief      initialize mpu_region_init_struct with the default values
    \param[in]  region_init_struct: pointer to a mpu_region_init_struct structure
    \param[out] none
    \retval     none
*/
void mpu_region_struct_para_init(mpu_region_init_struct *region_init_struct)
{
    region_init_struct->region_number        = MPU_REGION_NUMBER0;
    region_init_struct->region_base_address  = 0x00000000U;
    region_init_struct->region_limit_address = 0x00000000U;
    region_init_struct->instruction_exec     = MPU_INSTRUCTION_EXEC_PERMIT;
    region_init_struct->access_permission    = MPU_REGION_PRIVILEGED_RW;
    region_init_struct->shareability         = MPU_ACCESS_NOT_SHAREABLE;
    region_init_struct->attribute_index      = MPU_ATTRIBUTE_NUMBER0;
}

/*!
    \brief      initialize mpu_attribute_init_struct with the default values
    \param[in]  attribute_init_struct: pointer to a mpu_attribute_init_struct structure
    \param[out] none
    \retval     none
*/
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct)
{
    attribute_init_struct->attribute_number = MPU_REGION_NUMBER0;
    attribute_init_struct->memory_type      = MPU_OUTER_DEVICE;
    attribute_init_struct->inner_attributes = MPU_DEVICE_nGnRnE;
    attribute_init_struct->outer_attributes = 0U;
}

/*!
    \brief      configure the MPU region
    \param[in]  region_init_struct: MPU initialization structure
                  region_number: region number
                                 MPU_REGION_NUMBERn (n=0,..,7)
                  region_base_address: region base address
                  region_limit_address: region limit address
                  access_permission: MPU_REGION_PRIVILEGED_RW, MPU_REGION_ALL_RW, MPU_AP_PRIV_RW_UNPRIV_RO, MPU_REGION_ALL_RO
                  instruction_exec: MPU_INSTRUCTION_EXEC_PERMIT, MPU_INSTRUCTION_EXEC_NOT_PERMIT
                  shareability: MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_OUTER_SHAREABLE, MPU_ACCESS_INNER_SHAREABLE
                  attribute_index: attribute index
                                   MPU_ATTRIBUTE_NUMBERn (n=0,..,7)
    \param[out] none
    \retval     none
*/
void mpu_region_config(mpu_region_init_struct *region_init_struct)
{
    __DMB();
    /* select the Region number  */
    MPU->RNR = region_init_struct->region_number;
    /* disable the Region  */
    MPU->RLAR &= ~(MPU_RLAR_EN_Msk);
    MPU->RBAR = (((uint32_t)region_init_struct->region_base_address & 0xFFFFFFE0UL)   | 
                 ((uint32_t)region_init_struct->shareability << MPU_RBAR_SH_Pos)      |
                 ((uint32_t)region_init_struct->access_permission << MPU_RBAR_AP_Pos) |
                 ((uint32_t)region_init_struct->instruction_exec << MPU_RBAR_XN_Pos)) ;
    
    MPU->RLAR = (((uint32_t)region_init_struct->region_limit_address & 0xFFFFFFE0UL)      |
                 ((uint32_t)region_init_struct->attribute_index << MPU_RLAR_AttrIndx_Pos));
}

/*!
    \brief      configure the MPU attribute
    \param[in]  attribute_init_struct: MPU attribute initialization structure
                  attribute_number: attribute number
                                 MPU_ATTRIBUTE_NUMBERn (n=0,..,7)
                  memory_type: memory type
                                 MPU_MEMORY_DEVICE, MPU_MEMORY_NORMAL
                  outer_attributes: outer memory attributes
                                 MPU_OUTER_DEVICE
                                 MPU_NORMAL_OUTER_WT_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WT_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WT_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_NON_CACHEABLE
                                 MPU_NORMAL_OUTER_WB_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WB_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WB_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_RW_ALLOC
                  inner_attributes: inner memory attributes
                                 MPU_NORMAL_INNER_WT_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WT_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WT_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_NON_CACHEABLE
                                 MPU_NORMAL_INNER_WB_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WB_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WB_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_RW_ALLOC
                                 MPU_DEVICE_nGnRnE(for Device)
                                 MPU_DEVICE_nGnRE(for Device)
                                 MPU_DEVICE_nGRE(for Device)
                                 MPU_DEVICE_GRE(for Device)
    \param[out] none
    \retval     none
*/
void mpu_attribute_config(mpu_attribute_init_struct *attribute_init_struct)
{
    uint32_t attr_values;
    uint8_t  attr_x_value;

    __DMB();
    if(attribute_init_struct->attribute_number < MPU_ATTRIBUTE_NUMBER4) {
        /* configure MPU_MAIR0 */
        attr_values = MPU->MAIR0;
        attr_values &=  ~(0xFFUL << (attribute_init_struct->attribute_number * 8U));
        if(MPU_MEMORY_DEVICE == attribute_init_struct->memory_type) {
            attr_x_value = (attribute_init_struct->inner_attributes & 0x0CU);
        }else{
            attr_x_value = attribute_init_struct->inner_attributes | attribute_init_struct->outer_attributes;
        }
        attr_values |= ((uint32_t)attr_x_value  << (attribute_init_struct->attribute_number * 8U));
        MPU->MAIR0 = attr_values;
    } else {
        /* configure MPU_MAIR0 */
        attr_values = MPU->MAIR1;
        attr_values &=  ~(0xFFUL << ((attribute_init_struct->attribute_number -4U) * 8U));
        if(MPU_MEMORY_DEVICE == attribute_init_struct->memory_type) {
            attr_x_value = (attribute_init_struct->inner_attributes & 0x0CU);
        }else{
            attr_x_value = attribute_init_struct->inner_attributes | attribute_init_struct->outer_attributes;
        }
        attr_values |= ((uint32_t)attr_x_value  << ((attribute_init_struct->attribute_number - 4U) * 8U));
        MPU->MAIR1 = attr_values;
    }
}

/*!
    \brief      enable the MPU region
    \param[in]  none
    \param[out] none
    \retval     none
*/
void mpu_region_enable(void)
{
    MPU->RLAR |= MPU_RLAR_EN_Msk;
}

#endif /* __MPU_PRESENT */
__________________________________________________________________________________________________________________________
______________________TIMER_____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_timer.h
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_timer.c

fix reason: 
Delete asymmetric PWM related function.

V1.0.0:

V1.1.0:
#define TIMER_OC_MODE_APWM0                 ((uint32_t)0x00010060U)                 /*!< asymmetric PWM mode 0 */
#define TIMER_OC_MODE_APWM1                 ((uint32_t)0x00010070U)                 /*!< asymmetric PWM mode 1 */
__________________________________________________________________________________________________________________________
______________________RTC____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rtc.h

fix reason: 
Add Tamper1 and Tamper2.

V1.0.0:

V1.1.0:
Add
#define RTC_STAT_TP1F                      BIT(14)                                     /*!< RTC tamp 1 detected flag */
#define RTC_STAT_TP2F                      BIT(15)                                     /*!< RTC tamp 2 detected flag */
#define RTC_TAMP_TPxIE                    BITS(27,29)                              /*!< All Tamper interrupt enable */
__________________________________________________________________________________________________________________________
______________________RTC____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rtc.h

fix reason: 
Delete redundant function declarations.

V1.0.0:

V1.1.0:
Delete
/* set specified RTC tamper mask function */
void rtc_tamper_mask(uint32_t source);
/* tamperx event does not erase the RTC_BKP registers */
void rtc_tamper_without_bkp_reset(uint32_t ne_source);
__________________________________________________________________________________________________________________________
______________________RTC____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rtc.c

fix reason: 
Optimize function implementation.

V1.0.0:
void rtc_interrupt_enable(uint32_t interrupt)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    /* enable the interrupts in RTC_CTL register */
    RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_INT_TAMP_ALL);
    /* enable the interrupts in RTC_TAMP register */
    RTC_TAMP |= (uint32_t)(interrupt & RTC_INT_TAMP_ALL);

    /* enable the write protection */
    RTC_WPK = RTC_LOCK_KEY;
}
void rtc_interrupt_disable(uint32_t interrupt)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    /* disable the interrupts in RTC_CTL register */
    RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~(RTC_TAMP_TPIE));
    /* disable the interrupts in RTC_TAMP register */
    RTC_TAMP &= (uint32_t)~(interrupt & (RTC_TAMP_TPIE));

    /* enable the write protection */
    RTC_WPK = RTC_LOCK_KEY;
}
V1.1.0:
void rtc_interrupt_enable(uint32_t interrupt)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    /* enable the interrupts in RTC_CTL register */
    RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPxIE);
    /* enable the interrupts in RTC_TAMP register */
    RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPxIE);

    /* enable the write protection */
    RTC_WPK = RTC_LOCK_KEY;
}
void rtc_interrupt_disable(uint32_t interrupt)
{
    /* disable the write protection */
    RTC_WPK = RTC_UNLOCK_KEY1;
    RTC_WPK = RTC_UNLOCK_KEY2;

    /* disable the interrupts in RTC_CTL register */
    RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~(RTC_TAMP_TPxIE | RTC_TAMP_TPIE));
    /* disable the interrupts in RTC_TAMP register */
    RTC_TAMP &= (uint32_t)~(interrupt & (RTC_TAMP_TPxIE | RTC_TAMP_TPIE));

    /* enable the write protection */
    RTC_WPK = RTC_LOCK_KEY;
}
__________________________________________________________________________________________________________________________
______________________TRIGSEL____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rtc.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_rtc.c

fix reason: 
Add Tamper1 and Tamper2.

V1.0.0:

V1.1.0:
Add
    TRIGSEL_INPUT_RTC_TAMP1               = ((uint8_t)0xB1U),               /*!< trigger input source RTC tamper1 */
    TRIGSEL_INPUT_RTC_TAMP2               = ((uint8_t)0xB2U),               /*!< trigger input source RTC tamper2 */
__________________________________________________________________________________________________________________________
______________________TRIGSEL____________________________________________________________________________________________
Fix file:
../Examples/TRIGSEL/cmp_trigger_extout/main.c
ripheral/Include/gd32g5x3_rtc.c

fix reason: 
add systick configuration.

V1.0.0:

V1.1.0:
Add
    /* configure systick */
    systick_config();
__________________________________________________________________________________________________________________________
______________________LPTIMER____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_lptimer.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_lptimer.c

fix reason: 
Add Tamper1 and Tamper2.

V1.0.0:

V1.1.0:
Add
#define LPTIMER_EXTRIGGER_RTCTAMP1          CTL0_ETSEL(4)                       /*!< external trigger for RTC_TAMP1 input detection */
#define LPTIMER_EXTRIGGER_RTCTAMP2          CTL0_ETSEL(5)                       /*!< external trigger for RTC_TAMP2 input detection */
__________________________________________________________________________________________________________________________
______________________LPIMER____________________________________________________________________________________________
Fix file:
../Examples/LPTIMER/LPTIMER_decoder_mode/main.c

fix reason: 
Fix the error in gpio_config.

V1.0.0:
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_1);
V1.1.0:
    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_1);
__________________________________________________________________________________________________________________________
______________________CMP____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_cmp.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_cmp.c
../Examples/CMP/Blanking_output/main.c
../Examples/CMP/Interrupt/main.c
../Examples/CMP/NVIC_interrupt/main.c
../Examples/CMP/Port_output/main.c
../Examples/CMP/Timer0_CH0IC/main.c
../Examples/TRIGSEL/cmp_trigger_extout/main.c

fix reason: 
Format correct.

V1.0.0:
#define CMPx_INVERTING_INPUT_1_4VREFINT          CS_CMPXMSEL(0)                /*!< CMP inverting input 1/4 Vrefint */
#define CMPx_INVERTING_INPUT_1_2VREFINT          CS_CMPXMSEL(1)                /*!< CMP inverting input 1/2 Vrefint */
#define CMPx_INVERTING_INPUT_3_4VREFINT          CS_CMPXMSEL(2)                /*!< CMP inverting input 3/4 Vrefint */
#define CMPx_INVERTING_INPUT_VREFINT             CS_CMPXMSEL(3)                /*!< CMP inverting input Vrefint */

V1.1.0:
#define CMPX_INVERTING_INPUT_1_4VREFINT          CS_CMPXMSEL(0)                /*!< CMP inverting input 1/4 Vrefint */
#define CMPX_INVERTING_INPUT_1_2VREFINT          CS_CMPXMSEL(1)                /*!< CMP inverting input 1/2 Vrefint */
#define CMPX_INVERTING_INPUT_3_4VREFINT          CS_CMPXMSEL(2)                /*!< CMP inverting input 3/4 Vrefint */
#define CMPX_INVERTING_INPUT_VREFINT             CS_CMPXMSEL(3)                /*!< CMP inverting input Vrefint */
__________________________________________________________________________________________________________________________
______________________FFT____________________________________________________________________________________________
Fix file:
../Examples/FFT/fft_cal/main.c

fix reason: 
Modify the input data to be generated directly using the sin function.

V1.0.0:

V1.1.0:
Example implementation optimization.
__________________________________________________________________________________________________________________________
______________________HRTIMER____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_hrtimer.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_hrtimer.c

fix reason: 
Change the data type of cnt_reset in hrtimer_timercfg_parameter_struct, and modify the usage in .c file.

V1.0.0:
    uint32_t cnt_reset;                                                     /*!< the source triggering the Slave_TIMER counter reset, refer to: Slave_TIMER counter reset */
V1.1.0:
    uint64_t cnt_reset;                                                     /*!< the source triggering the Slave_TIMER counter reset, refer to: Slave_TIMER counter reset */
__________________________________________________________________________________________________________________________
______________________HRTIMER____________________________________________________________________________________________
Fix file:
../Examples/HRTIMER/HRTIMER_synchronization/main.c
../Examples/HRTIMER/HRTIMER_synchronization/readme.txt

fix reason: 
Bug fix, change HRTIMER_ST0CH1(PA9) TO HRTIMER_ST1CH0(PA10).

V1.0.0:
void gpio_config(void)
{
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_GPIOB);

    /* configure HRTIMER_ST0CH0(PA8), HRTIMER_ST0CH1(PA9), HRTIMER_SCIN(PB6) */
    gpio_af_set(GPIOA,GPIO_AF_13,GPIO_PIN_8);
    gpio_af_set(GPIOA,GPIO_AF_13,GPIO_PIN_9);
    gpio_af_set(GPIOB,GPIO_AF_12,GPIO_PIN_6);	
    gpio_mode_set(GPIOB,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_6);
    gpio_mode_set(GPIOA,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_8);
    gpio_mode_set(GPIOA,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_9);
    gpio_output_options_set(GPIOB,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_6);
    gpio_output_options_set(GPIOA,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_8);
    gpio_output_options_set(GPIOA,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_9);
}
V1.1.0:
void gpio_config(void)
{
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_GPIOB);

    /* configure HRTIMER_ST0CH0(PA8), HRTIMER_ST1CH0(PA10), HRTIMER_SCIN(PB6) */
    gpio_af_set(GPIOA,GPIO_AF_13,GPIO_PIN_8);
    gpio_af_set(GPIOA,GPIO_AF_13,GPIO_PIN_10);
    gpio_af_set(GPIOB,GPIO_AF_12,GPIO_PIN_6);
    gpio_mode_set(GPIOB,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_6);
    gpio_mode_set(GPIOA,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_8);
    gpio_mode_set(GPIOA,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_10);
    gpio_output_options_set(GPIOB,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_6);
    gpio_output_options_set(GPIOA,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_8);
    gpio_output_options_set(GPIOA,GPIO_OTYPE_PP,GPIO_OSPEED_100_220MHZ,GPIO_PIN_10);
}
__________________________________________________________________________________________________________________________
______________________CAN____________________________________________________________________________________________
Fix file:
../Examples/CAN/Pretended_Networking_mode/main.c
../Examples/CAN/communication_FDmode/main.c
../Examples/CAN/communication_classical_CAN/main.c
../Examples/CAN/communication_Loopback/main.c

fix reason: 
 Bug fix, to prevent CAN_TX from being accidentally pulled low.

V1.0.0:
    /* configure CAN0 GPIO */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11 | GPIO_PIN_12);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_11 | GPIO_PIN_12);
    gpio_af_set(GPIOA, GPIO_AF_9, GPIO_PIN_11 | GPIO_PIN_12);

    /* configure CAN0 GPIO */
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12 | GPIO_PIN_13);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_12 | GPIO_PIN_13);
    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_12 | GPIO_PIN_13);
V1.1.0:
    /* configure CAN0_TX GPIO */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_12);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_12);
    gpio_af_set(GPIOA, GPIO_AF_9, GPIO_PIN_12);

    /* configure CAN0_RX GPIO */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_11);
    gpio_af_set(GPIOA, GPIO_AF_9, GPIO_PIN_11);

    /* configure CAN1_TX GPIO */
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_13);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_13);
    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_13);

    /* configure CAN1_RX GPIO */
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_12);
    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_12);
__________________________________________________________________________________________________________________________
______________________PMU____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_pmu.h
../Firmware/GD32G5x3_standard_peripheral/Include/gd32g5x3_pmu.c

fix reason: 
Add function pmu_ldo_output_select.

V1.0.0:

V1.1.0:
Add
/* select LDO output voltage */
void pmu_ldo_output_select(uint32_t ldo_output);
__________________________________________________________________________________________________________________________
______________________EXTI____________________________________________________________________________________________
Fix file:
../Examples/EXTI/Key_external_interrupt_mode

fix reason: 
Add function.

V1.0.0:

V1.1.0:
Add file
../Examples/EXTI/Key_external_interrupt_mode/main.h
../Examples/EXTI/Key_external_interrupt_mode/systick.h
../Examples/EXTI/Key_external_interrupt_mode/systick.c
__________________________________________________________________________________________________________________________
______________________ADC____________________________________________________________________________________________
Fix file:
../Examples/ADC/ADC0_ADC2_temperature_Vref_Vbat/main.c

fix reason: 
Delete function.

V1.0.0:

V1.1.0:
Delete
    /* ADC software trigger enable */
    adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL);
    adc_software_trigger_enable(ADC2, ADC_INSERTED_CHANNEL);
__________________________________________________________________________________________________________________________
______________________VREF____________________________________________________________________________________________
Fix file:
../Firmware/GD32G5x3_standard_peripheral/Source/gd32g5x3_vref.c

fix reason: 
Bug fix.

V1.0.0:
void vref_voltage_select(uint32_t vref_voltage)
{
    /* clear old value */
    VREF_CS &= ~(uint32_t)VREF_VOLTAGE_SEL_2_048V;
    VREF_CS |= (uint32_t)vref_voltage;
}
V1.1.0:
void vref_voltage_select(uint32_t vref_voltage)
{
    /* clear old value */
    VREF_CS &= ~(uint32_t)(CS_VREFS(3));
    VREF_CS |= (uint32_t)vref_voltage;
}
__________________________________________________________________________________________________________________________